Tuesday, November 29, 2016

Board ready but USB cable issue, finished coding emulator role


This morning I installed the cables on the Diablo disk drive and hooked up the fpga. It was still loaded with the prior bitstream, but the changes in this interface require an update. Among other changes, this version of the board has active SelectUnit1 and ReadGate signals, reads the SectorNumber from the drive and does not receive IndexMarker.

First up should be a test with the drive powered but not fully spinning, so that I can verify that key signals such as WriteGate are not asserted.  I did this and did verify those signals, but found other issues.
New board attached to FPGA
I couldn't find my original USB cable that connects the FPGA board to the PC, it disappearing during the holiday storage, but I substituted another I found. The connection is erratic, leading to random resets, spurious data transfers and likely unrequested transaction initiations. That isn't safe with the drive spinning, so I need to resolve this before doing anything else.

I concluded the coding of the emulator task with the process to write one or more records on the current sector. It was synthesized and set up to begin testing of the emulation function, initially with the stubby monitoring board attached to the fpga board. This will let me inject given inputs and watch the outputs with the scope and logic analyzer.

Stubby board to allow easy access to inputs and outpus

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