On the design front, I worked on the logic for the emulator role where it will handle WriteGate switching on. This occurs in two cases - when writing an entire sector of three records from scratch or when updating the later records within an existing sector.
The process that is continually reading sectors should continue to run, but its control of the RAM blocked whenever WriteGate is on. The reading process lets us know which record we are in, essential for the writing process to properly address RAM locations.We don't, however, need to be absolutely synchronized to when the read thinks it is in preamble, postamble, sync or specific words of a record.
The write process will decode the incoming WriteData&Clock signal to follow but throw away the preamble and sync word, before capturing and writing the header, label or data record words into RAM. It will verify checksums just for completeness although there is nothing appropriate that the emulator can present back to the Alto if the checksum does not match.
The write process will then follow and throw away the postamble of the record it is writing. If there are more records in the sector to write, it will iterate until done with the data record. A bit tricky to set up but will work on it after I set up the test bed again.
I felt it time to switch over and test the second version of the driver role interface board I had built, the one I will be passing along to Al Kossow once we are done with our testing on the restored Alto. I performed one more continuity/shorts/wiring test then populated the chip sockets and began circuit tests.
With power applied but the fpga and disk drive unconnected, I began to inject voltages to each side in order to check that the appropriate results appeared on the other connector. Only when these are judged correct would I cable everything together to test out some reading and writing.
Ended the day chasing some peculiarities, thus no full test yet.