After replacing the bad 74LS05N chip, I repeated the test to verify that the BACKWRAP output signal would float high if hooked to a suitable pull-up resistor, while the machine was in the idle (REST) state. That did not happen, and it appeared to be the fault of the the same gate. It had a low input, open collector inverter gate with a pullup resistor on the output. This should result in a high output.
Suspiciously, the resistance from the output pin to +5V was measured as 5K but the resistor is marked 10K. This leads me to think that a trace is shorted to some other trace with a 10K resistor as well, producing the reading I found. If the other trace is another open collector output that is pulled to ground, it would match the behavior I saw.
I have been testing connectivity to every pin as I solder in the replacement chips, but that won't show me shorts to additional traces. I will have to find it by trial and error, coupled with hints from the schematics such as OC gates with 10K pullup resistors.
The board has 90 chips, quite a few capacitors and so forth, plus a ton of resistors. The location of the resistor on the PCB is almost random, often nowhere near the chips it is connected to. Further, the numbers hop around randomly by location. It forces me to carefully search the board for each resistor I want to locate, wasting significant time.
To make this easier, I decided to use a high res picture of the board in order to build a spreadsheet for all the components. The chips are labeled strictly by their physical location on the board, but nothing else is so conveniently numbered. The chip rows are numbered 1 to 6 and the columns are labeled A through J.
Therefore I will apply that location scheme to my spreadsheet. Parts below row 1 of the chips are in component row 1, parts between rows 1 and 2 are in component row 2, and component row 7 is for parts above the top row of chips. When a part is to the side of a column letter, I will use the letter to the left of the part. Any part to the left of the J column will be marked as component row K.
My first pass looked at components on the board, placing them in their site by the scheme above. The second pass covered the five pages of the schematic, identifying each component with its page number and approximate spot on the page. I used a Left-Center-Right and Top-Middle-Bottom grid for the schematic locations.
I was left with a few components I could see on the board but not on the schematic. Other components were drawn on the schematic but no visible on the board. I suspect a version mismatch between the board and the schematic. The first signal I traced out which had components on the schematic but not on the board was an input line that had a series resistor and capacitor to ground, intended as a debouncer, but beeping the circuit showed that the input line went directly to the gate. Thus, I will have to contend with the documentation mismatch.
I began a very tedious process of beeping out all the connections between the chips and to the input/output pads. With 90 chips having an average of 14 pins, plus a couple hundred non-chip components on the board, there was a lot of testing to complete. In many cases, one of the pins is fed or leads to a part on a different schematic page, so flipping and recording of source/destination is necessary.
I began randomly with schematic page 2. I realized that once I had tested all the off-page connections from this page, they were tested whenever a signal ran from another page back to 2. This will speed up my page flipping as I advance through more completed pages.
More discrepancies between the schematic and the board arose. For example, when the loading state machine enters the Wrap state, a timer was triggered that on the schematic had a 15K resistor and 100uf capacitor, but on the board I found a 470K resistor and 2.8 uf capacitor. Those combinations are about the same RC constant although with very different currents during charging.
It took me about two hours to complete 1/3 of a schematic page, thus a linear extrapolation would put the remainder of the task at 28 hours work. Some of the pages are sparser and there will be the speedup effect dealing with off-page connections to pages I have already completed, but a conservative estimate is another 2 or 3 days elapsed time.
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