Detailed study of logic analyzer trace, one signal issue spotted, then OneDark failure returns

 REVIEWING EVERYTHING IN THE LOGIC ANALYZER TRACE

I returned to the shop this morning and opened the trace I had captured previously. This time I looked through it in complete detail, assuring myself that every signal operated at the proper time and with the correct values. Some important information wasn't captured - signals such as IM that go out on the interface are not carried on the motherboard, and the depth of the logic analyzer memory wasn't sufficient to record all 80 data columns plus the leading and trailing portions of the card. 

ONE SIGNAL DID NOT SHOW UP AS IT SHOULD HAVE

Everything that was captured looked great with one exception. Three of the four clock phases are gated at specific times as ST0B, ST0C and ST0D to control the latching of the value of each column. I see ST0C and ST0D occuring at the right time, but ST0B should have been active in the immediately preceding clock interval but was missing. 

The schematics show that there are only two gates involved in converting the phaseB clock signal to ST0B - an inverter and a NAND gate. I did tack a wire to the two pins of the inverter gate and verify that the phaseB signal is passing along nicely.

Here is where it gets interesting. ST0B and ST0C are produced by two NAND gates in the same chip, driven by a common signal from a comparator. When the offset count from a wheel tooth matches the calculated offset value, the three signals ST0B, ST0C and ST0D are passed along. Since ST0C is showing up, the common signal from the comparator is working correctly.

The obvious conclusion is that the NAND gate is defective that generates ST0B. I tacked on wires to confirm however the old OneDark error came back, which blocks the receiver from processing cards, calculating offsets or generating the signals. I have to go back and get that solidly repaired before I can continue.

ONEDARK PROBLEM INVESTIGATION

If you remember from an earlier post, the machine had OneDark active even though there was no card in the path and all twelve photocells should be registering light. When I isolated the photocell components and checked them, I had found that rows 8 and 9 were not switching fully on with light. Its voltage was in the forbidden zone that caused the logic gates to misread the state. 

I tweaked the current to the LEDs until the phototransistors developed good voltages. This allowed me to capture the logic analyzer trace that I did. Now the issue seems to be back. I decided to tack on wires for several rows of the phototransistor emitter lines and verify the voltages. 

OOPS

Somehow in the process of inserting the Control PCB with the tacked wires, I think I shorted the 5V power lines because the logic power is gone. At this point I left for the day before I made any more mistakes. It was a long night and I had a hangover today.