LIMITATIONS OF IBM STORAGE ACCESS CHANNEL
The Storage Access Channel (SAC) feature for the IBM 1130 gives support for a wide range of peripheral devices to be attached to the 1130 CPU, as it offers access to memory, interrupt levels, cycle stealing and other status information necessary to create a device controller for any type of XIO operation.
Devices supported through the SAC, either attached to the 1133 Multiplexor box by SAC or directly on the connector, include 2250 graphic terminal, 1403 line printer, 2501 card reader, 2420 tape drives and disk drives such as 2310 and 2311.
The IBM 1130 has six interrupt levels, 0 through 5, but the SAC from IBM only supports putting devices on interrupt levels 2, 3, 4 or 5, not the two highest priority levels. Some peripherals, such as the 1132 printer and 1442 card reader/punch, make use of these interrupt levels. Since IBM includes controller hardware for these peripherals inside the 1130 CPU frame, they would never be attached through a SAC.
However, I want to be able to operate with virtual 1442 and 1132 devices, reading punching and printing with PC based files instead of real cards or paper. I had to resolve this deficiency to make full use of my expander box for the 1130.
MY ADDITIONAL CABLE TO AUGMENT THE SAC FEATURE
I designed and built companion circuits that allow me to see and request interrupt levels 0 and 1. This is accessed by an additional cable I built and a small interface board installed inside the 1130.
I also use this cable to route a control signal to trigger a program load sequence from my expander box. That is, it will sequence the switching as if the operator pushed Immediate Stop, Reset and then Program Load in succession. This is done with a small state machine and some relay switching of the wires that run to the console pushbuttons for those operations.
BUILT CONNECTOR ON MY NEW FPGA EXPANDER BOX FOR THE ADDITIONAL CABLE
I made use of a 3x3 connector pair to hook up the five signals that run over my additional cable, allowing me to detach that cable just as I can detach the power and SAC signal cables. To be sure I had it wired correctly, since this doesn't exist in the IBM diagrams and documentation, I carefully traced out and documented my augmented capabilities right from the 1130 logic circuits through the interface boards, cable and connectors up until the FPGA input or output terminals assigned to the signals.
As part of this work I will clean up the interface board implementation and mounting inside the 1130, now that I have good schematics and notes on everything involved with that cable.
TESTING THE IOB6120 BOARD, WITHOUT POWER
There is quite a bit of testing that can be done to a complex board like the IOB6120 before you apply power to it. Simple tests like resistance between VCC and ground rule out gross shorts. I then checked that the power and ground was delivered properly to all the ICs on the board. I chose some signal paths and verified good continuity between the pins of the two ends. During this process I discovered a flaw in the PCB.
IOB6120 BOARD REVISIONS AND REWORK ACCORDING TO OTHERS
There is a second version, Rev B, that is said to correct a design flaw that leads to rapid depletion of the backup batteries which preserve data in volatile memory devices. The cause of the depletion was said to be due to back flow of the battery current into a chip that is not part of the nonvolatile memory system. The solution to this was the creation of diodes with pullup resistors to isolate the chip enable lines of the nonvolatile chips from the enable driver chip - a total of four diodes and four pullups.
Revision B has this implemented while the original does not. A rework is possible by cutting the chip enable traces, tacking on a diode and pullup resistor then routing VCC to the other end of the pullup resistor. I was prepared to make this change to my board, but discovered something during my bench validation of the board which I believe was missed by others.
The original board failed to route VCC to a pin of one IC, a BQ2201 nonvolatile memory controller chip. This device is connected to the battery backup voltage as well as the power-on VCC rails. It compares the voltage and will block the chip enable to the volatile RAM chips if the VCC drops below 4.67V. It also switches the two coin sized backup batteries onto the power rail for the RAM chips.
With this unpowered, the chip will ALWAYS block the chip enable and hook the batteries up to power the circuit. That chip enable gates the 3 to 8 demultiplexer so that the board should not be able to work at all with that trace unconnected. I soldered in a jumper to deliver power to the pin - and do see that the rev B correctly routes power to it.
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| Jumper bringing VCC to IC14 - BQ2201 |
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