Verified that my plan F connectivity will work using small focused test

ACCESS METHOD FOR THE FIVE NEW SIGNALS

These signals are controlled by Peripheral Input Output (PIO) blocks which are memory mapped into the HPS to FPGA Lightweight (H2FLW) bridge at relative addresses 0x00000100 - 0x00000107 and 0x00000200 - 0x00000203 with each PIO implementing four 32 bit words. I built the PIOs to control 3 and 2 bits respectively. 

The four words and their purpose are:

• Data register - writing to this register sets the state of the output bits, reading fetches input values
• Direction register - a 1 bit sets the associated signal to output, otherwise it is an input
• Interrupt register - one function of PIO is to generate interrupts, but I am not using them
• Edge Capture register - bit set if a falling edge was detected on the signal since it was last reset

I already have a memory mapped pointer to the H2FLW bridge area, thus to see if an edge capture was detected I would read BRIDGE_AREA + 0x00000103 and look for a 1 bit in the word at the bit position associated with the desired input signal I am watching.

To turn on the LCD Reset signal, which is one of the two outputs, I would write a 0 to BRIDGE_AREA + 0x00000200 since this reset signal is active when low. Writing a 1 there will turn off the reset.

These five signals are routed to the DE10-Nano external GPIO 0 connector for signals GPIO22 through GPIO26. All I need to test is to hook up a jumper for each of the three input pins to ground and then 3.3V while verifying that I see the right value. Then I write a 0 and then a 1 to the two output pins while checking the voltage with a VOM. 

TEST RESULTS ARE STELLAR

Everything worked exactly as expected. I was able to read the states of the three input signals. When any of the signals took a transition from 1 to 0, the edge capture was captured and could be read when I accessed the register. Resetting the edge capture bit cleared the state as expected. The two output signals could be set to 0 or 1 with no impact on the others. 

WHAT IS NEXT ON THE TESTING SCHEDULE

I will modify and rerun my simple test to verify that the commands that go over the H2FLW bridge to my main logic still work correctly, in spite of various accesses to the PIO blocks. I expect there is no chance that this won't work properly, but testing at this stage is better than chasing a bug in a more complex test later. 

I will wire up the LCD module to the DE10-Nano board with the appropriate new signals as well as the original SPI wires. My test program will work out how to communicate with and control the LCD monitor controller and later the touch screen controller. 

I set the SPI to 8 bit words to better fit with how the Raspberry Pi Nano did things. I am using an inverter on the slave select line and configuring this as mode 2 rather than the real mode 0, in order to keep the SPI logic in the DE10-Nano from dropping slave select between bytes. 

From my review of the schematic and other literature I am relatively sure that it won't matter if my SPI link drops the select between groups of double bytes or at any slowdown - that the slave select behavior will not be critical to proper operation. As I test I will verify this and if for some reason I have to manually control slave select, I can expand the PIO output block to make this happen and then go back to mode 0 SPI. 

My code writing to SPI has to carefully check that transmit buffers are empty and we are not busy before I drop slave select, but that is really just good practice for driving an SPI link.