CLUE TO BE CHASED
After interminable permutations of configuring the U-boot and testing I was looking very closely at the SPL (preloader) since that is what should execute to the point that see messages on the console, but it does not. In the directory where the SPL is built a noticed a subdirectory DTS and looked into it.
There is a device tree blob in there, dt-spl.dtb, which when I converted it to source format had no entries at all describing the SDRAM on the board. Without RAM, the SPL will fail quickly. It runs from some limited memory on the board, initializes the regular RAM and copies itself to RAM to continue. If the RAM configuration is incorrect then SPL cannot get very far.
This sounds like the root cause of the completely silent behavior of every SPL I generate, regardless of which of the newer U-boot source versions I use. I will dig into how this is generated during the make process and see if there is a missing file or a failure I can detect somewhere in this godawful toolchain.
Somehow I detect that absolutely NOBODY tried to generate U-Boot for the Terasic DE10-Nano board in recent years, in spite of Intel having changed their embedded generation process and tools many many times and in spite of many newer versions of U-boot having been released. Nobody responsible or cared enough to try. Since almost every user of these boards that posts videos or blogs simply follow the reference examples exactly, they don't have to address U-boot and therefore don't stumble over the problem.
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