DIABLO 33 DRIVE WITH STANDARD DENSITY HEAD ON HAND
The Diablo 33 drives were widely used for minicomputers and other systems, derived from the IBM 13SD (2310) disk drive developed for the IBM 1130 system. However, quite a few enhancements were included in these drives (and similar derivatives like DEC RK-05), including direct seek to a target cylinder and single command restore to home position.
The most important change that most implemented as to double the recording frequency, thus doubling bit density and cartridge capacity. On the IBM 1130 (13SD drive) the bit cell frequency is 720KHz, while the RK-05 and others use 1.44MHz. Thus a 2315 cartridge holds just 1MB at 720KHz but 2MB on the RK-05 (and others).
The higher frequency uses a different recording/playback head, ceramic surface, while the IBM heads are chromed metal surfaces. The ceramic heads are more resistant to scratching from transient head/disk interference (such as a tiny dust particle slamming between head and disk), these can generally be cleaned well and put back into surface, whereas the metal surface slowly accumulates scratch lines until its aerodynamics are too spoiled for safe use.
Diablo offered the model 33 in both standard and high density flavors, which are 720KHz and 1.44MHz bit cell rates. For the standard density they use chromed metal heads just like the IBM drive. I am fortunate enough to own a standard density model 33, although its heads had been badly scratched due to a crash before I acquired it.
I am now able to replace the heads with standard density heads in good enough condition to fly. Thus, I plan to use this drive as a means of reading and writing 2315 cartridges containing IBM 1130 software.
ARCHIVER DESIGN BEING BUILT BASED ON DIGILENT ARTY A7 BOARD
I had a spare Arty A7 board, based on a Xilinx Artix 7 chip (xc7a35ticsg324-1L) and a 128MB DRAM. It has enough general IO connections to drive the Diablo for an archiving session, enough RAM to grab an entire 2315 cartridge in one pass, and a serial link over USB where I can send out the data once the archiving has completed.
I am finalizing my testing of the DDR interface, ensuring I can reliably write and read to the RAM, before I move on to testing the rest of the design. The IP generation in Vivado provides an example program that does this satisfactorily, so I just loaded that into the board and watched the LEDs to see it perform.
OVERALL LOGIC OF THE ARCHIVER
The archiver opens a serial port link to a remote host and waits for a simple command to start archiving. The drive comes ready with the arm at home (track 0) position. The logic will step through the 203 cylinders one by one, performing a one track seek between each. For each cylinder, it will step through both the top and bottom heads (two disk surfaces). For each head, it sequentially reads and saves sectors 0, 1, 2 and 3.
The read logic will be set up when the target sector is approaching the read heads and given a read request. When the sector pulse from the drive arrives, the read gate is turned on and we begin to receive streamed bits on both read_data and read_clock lines.
Every sector begins with a bit less than 200 bits of zero, which ensures the drive can correctly separate the clock and data pulses coming from the head and route them out on read_clock and read_data lines. The first nonzero bit is the sync word, a special value of 0x8000 that is used to identify where each 16 bit word begins. The 1130 stores words with the high order value labeled as b0 and the lowest order value at b15, thus the one bit coming in on read_data is for b0 of the sync word.
The actual data recorded on the cartridge is 20 bits long for each 16 bit 1130 data word, tacking on four error detection bits after b0 is read in. The stream of 20 bits is b15, b14, b13 . . . b0, e0, e1, e2 and e3. The error detection scheme is simple, based on counting how many one bits were received in each word. As long as the count of one bits received, after we accept all 20 bits from the disk head, is an even multiple of four, then we have a good word. Formally this is 0 modulo 4, implemented by the counter built from two bits so it is always modulo 4.
The sync word has only a single one bit thus it needs to send three more to get our counter to 0b00 for a good status. Bits e0, e1 and e2 should be a value of 1 each, with the final e4 bit always a zero. We validate the sync word was properly formatted otherwise anything we try to extract in the sector will not be correct. The syncerror flag is raised if the error detection fails on the sync word.
After each read_clock bit of 1, we see if a 1 bit comes in on read_data in the interval before the next read_clock bit. If it does, we saw a one value, otherwise the data value for this bit cell (combination of a clock pulse and either a data pulse for 1 or absence of a data pulse for 0) is a value of zero. In any case, after each read_clock pulse (1 bit arriving) we push the captured value into a shift register.
Physically on the disk the low order data value arrives first, with b0 at the end, so we push into the shift register to produce an 1130 format value b0 to b15 once all 16 bit cells have arrived. Any time a one value was pushed into the shift register, we increment the error detection counter. This continues for the last four values, e0 to e3. After the 20th bit value was received, if the counter is not 0x00 (or rolled around to 0b00) we raise the ECCerror flag.
The 16 bit value from the shift register is written to the ram and our word address bumps up by 1 (having started at 0). When we have read all 321 words - a full sector - we raise a done flag so that the archiver can advance to the next sector.
Once all 203 cylinders are read and in RAM, we write the data values over USB serial link to a remote system where the data can be captured and postprocessed to build a virtual 2315 cartridge file.
