Designed replacement 5806223 card - device controller logic for the 1627 plotter attached to an IBM 1130

BASED ON BREADBOARDING TESTS, I DEVELOPED A COMPLETE SCHEMATIC

I tested my plan to use monostable oscillator chips to get the same behavior as IBM's AC triggered gates. IBM uses these, which emit a short pulse at the falling edge of one signal as long as the enabling signal is also on. This allows IBM to interface to external devices without the challenges of metastable behavior that can occur with clocked digital electronics.'

The IBM gate emits the pulse and it turns a flipflop on or off, with no clock on the flipflop and no relationship to the 1130 system clock. In addition to its use with signals outside the 'clock domain', it is also widely used to activate flipflops in many situation inside the CPU logic. 

Its primary use on this card is to set flipflops for particular bits that were set by the user as part of their XIO Write instruction. The gate uses the bits as the enabling input, and the falling edge that activates it is from a NAND gate that turns on (goes low) when we have an XIO Write to Area 5 (the plotter) at clock step T6. 

The controller logic uses pairs of single shots in series, which emit a low signal for a fixed duration. For movement of the pen on the paper, the first SS fires for 2.5 ms when its input goes low. As its output goes low for that first SS, it sets the busy condition. The inverted (high) output of the first SS is hooked to the second SS, so that when the first SS time period expires, the output goes low and triggers the second SS for another 2.5 ms. 

As the second SS goes low, it triggers an AC gate to reset the that held the pen motion bits. The low state of the second SS also drives the busy status of the plotter. When the second SS interval expires, the busy condition goes off; the falling edge triggers another AC gate to turn on a flipflop called Response. When Response is on, it drives a request for an interrupt on level 3. 

As you can see, the design depends very heavily on these falling edge detecting gates. I know that the monostable oscillator (single shot) chips have multiple control inputs one of which can act as an enable. Thus, using the 74LS122 with the B bit as the enable and the NAND gate for the XIO write as the trigger will produce a pulse in the range of 30-35ns if enable is high when the trigger edge drops. 

I also made use of 74LS74 flipflops but not in the clocked style they are normally used. I used the asynchronous set input to turn them on when my 74LS122 produces its pulse, and use the async clear input to turn them off when the second SS expires. This takes up more real estate than modern combinatorial gates and flipflops, but it behaves as the IBM circuit does. There is a NAND gate for the XIO Write, a 74LS122 to act as the AC trigger gate, and a 74LS74 flipflop that is set by the pulse from the trigger. 

FAIRLY DENSE BOARD - 22 INTEGRATE CIRCUITS PLUS PASSIVE COMPONENTS

Surface mount chips give me two flipflops per package and four NAND gates per component, but 74LS122 is its own chip. Overall I need ten chips for the single shots, plus four chips for the flipflops. The remainder are the gates that detect when an XIO Sense DSW is issued to feed the appropriate status bits, to detect the XIO Write when we are commanded to move the plotter, and all the other functions. 

The movement commands set for flipflops for up, down, left and right. These use the pair of SS with 2.5ms timing. In addition, the programmer can raise the pen off the paper or lower it down. Those operations take two more flipflops and their own pair of SS since they require 50ms per SS due to the slower mechanical motion. The four SS with fixed times (2.5 or 50ms) require an external resistor and capacitor for each to determine the timing. The SS acting as AC gates operate without external components. 

The 1627 is driven by a 12V signal that is normally high, but pulled to ground for the 2.5 or 50ms of the first SS in a pair. This trips circuitry inside the 1627 to advance the stepper motors one position. This board has open collector gates to drive those signals, with pullup resistors hooked to the 12V power rail. The outputs to the IBM 1130 are inverted logic signals -Req IL3, -DSW Bit 0, -DSW Bit 14 and -DSW Bit 15. These are pulled low by open collector gates on this board. The pullup is done in the 1130 not on this card so no resistors are needed for those outputs.

The design checks for a powered up plotter by sensing the -24V supply from the device. This is hooked to a resistor voltage divider with the upper end hooked to +12V. Thus, the condition being sensed is either 12V if the plotter is turned off or a negative voltage if it is turned on. Modern gates don't like such voltages, so I whipped up a circuit that produces either 5V or barely negative. Using a diode and current limiting resistance ensure that the gate sensing this won't be damaged by the presented voltages on its input. 

Finally, the 5V logic chips on the board are powered by a LVDO voltage regulator that drops the 12V input on the card down to the 5V we require. 

MECHANICAL CONNECTION - SACRIFICIAL DOUBLE WIDE SLT CARD

The double wide SLT card is 3" high and 3.25" wide, with its twin 2x12 sockets that plug into the backplane. My PCB is a bit smaller and will mount atop a card that has been cleared of components and readied for attachment. Small jumpers are soldered to the PCB and the connectors of the board. 

FINALIZING THE PCB LAYOUT WHILE I BREADBOARD AND TEST THE DESIGN

I am mostly done laying out the PCB with the circuitry. When I am comfortable that it will work properly I will send it out to the fab to make five boards. During the wait I will buy all the SOIC-14 sized ICs and other components to solder on the board. 

I will continue to put together DIP sized chips to verify each part of the design before committing to build the cards, using my breadboard testing gear and monitoring timing on the scope. 

Fixed pins on backplane allowing card insertion; working with another museum on a replacement card for 1627 plotters

BENT PINS STRAIGHTENED ENOUGH TO LET THE SLT CARD SNAP INTO THE SOCKET

I worked on the pins slightly and was able to insert the card properly into the slot that had the damage. I was worried that the pins might have broken off but I did manipulate them as gently as I could, as few times, which ultimately succeeded. This resolves one of the mechanical issues that was outstanding for the restoration. 

1627 PEN PLOTTER CONTROLLER LOGIC IS ONE SLT CARD - 5806223 - THAT NOBODY HAS

I know of two museums that have plotters but lack the card that interfaces it to the 1130. I too have a 1627 (needing restoration) but lack the card. This was the subject of recent conversations with peers restoring systems in Europe.

The 6223 card is a double card, taking two slots vertically on the backplane. The ALD pages identify the functionality of the card, which should be relatively easy to replace. Ideally the solution will plug into the same backplane slots as the IBM card, with bonus points if it has a compatible appearance. 

This logic makes use of the IBM edge triggered (what they call AC trigger) gates and flipflops, which don't have any modern equivalent gate. I am exploring various circuits using (relatively) modern TTL gates that might fit in the footprint of the 6223 card. Another option is to use a mini FPGA board, several of which will fit with room to spare. This allows room for some interface circuits to deal with the 12V, -3V, -24V and other funky signal voltages present when working with the 1130 and 1627. 

I began breadboarding and testing circuits using 74LS121 monostable oscillators (one shots) to act as the IBM edge triggered gates, turning 74LS74 flipflops on and off. I will continue to build out the circuit using these SSI and MSI TTL devices, then try to fit them all within the area of the 6223 card surface using surface mount chips. If that works I can whip up a PCB design and order the parts. 

The FPGA version is much easier, the only challenge is keeping the height of the FPGA board small enough so that the card can fit side by side with ordinary SLT cards in the gate. 

Mechanical work on VCF 1130 today

TESTING DEVICE CONTROLLER LOGIC WHEN I FOUND DAMAGE TO THE BACKPLANE

I pulled a card and couldn't insert it into the backplane reliably, so when I inspected I found that two pins were bent. The plastic cover over the card end had cracked and had other damage that led to this. While I bent them back correctly to the eye, cards still won't snap in. This will be fun, I can see. 

I will continue to adjust the pins and work on getting the card to seat properly. I replaced the plastic cover from a spare SLT card, manually marking the card number. Hopefully I will get everything repaired. 

FINALLY REMOVED BLOWER CAGE FROM MOTOR SHAFT

The blower motor which produces the high volume of air through a HEPA level filter to float the recording heads over the disk platter was not working. I identified that one of the wires to the motor was an open circuit. Dismounting the motor from the drive was easy, but the blower cage and rotor was almost welded to the motor shaft. 

The removal of the setscrew should have allowed the rotor to slide off, but it was almost beyond my ability to get it off.  Since the hub was inside the rotor cage, a traditional pulley would not fit inside. I had to partially disassemble the motor to be able to put enough torque on the shaft to help dislodge it.

I had to scrape some corrosion off the end of the shaft and use clock oil in order to get it to move better. Finally with some vice grips on the hub and lots of effort, I got the shaft to come out. Now the motor needs to be repaired or replaced. 

LOOKING FOR EASY FIX FIRST

I was hoping that I had a break in the wires, as they were shielded inside woven metal and an outer plastic cover. Alas, I confirmed that the break is inside the motor. All my inspections failed to uncover an obvious point of the failure, thus there is no hope of a surgical fix. 

THINK I FOUND A CLOSE MATCH ON EBAY TO REPLACE THE DEAD MOTOR

The motor was built by Robbins & Myer. The data plate show that it is a single phase motor, 1/30 horsepower, turning at 3450 RPM. The frame type is F26 which indicates the physical dimensions of the motor and shaft. 

I looked on eBay and found a very similar motor advertised. It is the same frame type F26, spins at 3350 RPM which is close enough as this only moves air. The other difference I see is the type is KP whereas the disk drive motor is KS. I suspect the difference in speed is the reason the type varies.

 

According to the listing, this was pulled from a Bell & Howell 16mm projector, but is working. It appears to be a nice drop in replacement and I should receive it within the week. 

2310 emulation write module rewritten and successfully simulated

BUS WRITE STEPS THROUGH A FEW STATES WHEN THE WRITE GATE IS ACTIVATED

Write gate signal starts a write. The erase and write heads are turned on and the drive begins sending out the 720 KHz  clock as it is writing each bit cell. This should continue for the remainder of the sector. The state machine stages are idle, preamble, sync word, data write, and postamble. 

The preamble is 250 microseconds of zero bit values written to the drive. Each bit value is recorded with one clock bit and one data bit each in a 720 nanosecond interval. Recording a bit is accomplished by reversing the flux of the write head. Thus in each clock bit interval the flux is reversed, but in the data interval it only reverses if the bit value is 1, otherwise the flux remains unaltered. 

The preamble is thus 250 us of alternating flux reversal and no flux reversal (writing zero bits). The drive synchronizes a kind of phase locked loop to the clock bits during the preamble thus it can know which pulse is a clock bit and which pulse is a data bit value of 1. The drive and the controller logic now sees clearly delineated clock and data bits, but the controller must also know which bit cell is the start of each word on the disk. 

The sync word serves this purpose. A flux reversal during the data interval signals a 1 bit and the end of the preamble. The 1130 architecture is 16 bit words, but the 2310 writes these on disk as 20 bits, the first 16 are the data and the next four are a check pattern to detect errors reading the disk. Every time a 1 data value is written in the word, a two bit counter is stepped. 

The goal is that the counter will be at zero at the end of a valid word. Thus if a word already has four, eight, twelve or sixteen bits that are 1, the four check bits are written as 0000. However, if the two bit counter is not yet zero, the drive will write a 1 bit and bump the counter until it reaches zero. Thus with three bits that are 1, the check bits are 1000. With two bits in the word that are 1, the check bits are 1100. With one bit that is 1, the check bits are 1110. 

The sync stage will write 11110 which is for a word of 0000000000000001 with the check pattern 1110 appended. Following this the controller is synchronized on the start of each word - the next bit cell is the first bit of data word 1 of the sector and the state machine moves to the data stage.

In the data stage, we collect the bit values coming from the controller into groups of 16, then absorb and validate the four check bits. This 16 bit value is written to the DRAM of the emulator and we start with the next word. A sector on the 2310 is up to 321 words long, so we loop while counting words. If the write gate is dropped by the controller (writing a short sector) then we move immediately to the final postamble stage, otherwise we move there are the count of 321 is completed.

The postamble writes more words of zero until we reach the end of the sector. Once the new sector arrives the state machine goes back to idle and waits for a new write gate signal. 

TRICKY PART IS DEALING WITH THE CHECK BITS WHICH ARE NOT STORED ON DRAM

The configuration values for the emulator are set for 16 bit words, which ignores the 4 check bits that occur after each word. In the RK-05, there are no check bits after each word so the logic of the emulator is directly based on bit and word counts for a sector. A checksum word follows all the data words on the RK-05, a different and improved error detection scheme from that of the 2310. 

I have to introduce separate action that does not step certain counters during the final four bit cells, while ensuring that the emulator doesn't stop the read or write prematurely because it thinks all the bits have arrived correctly. For example, the emulator calculates a sector as 5, 136 bit cells long, not counting preamble, sync or postamble. 

If you use the bit cell duration of 1.4 microseconds with that value, you would consider a sector complete at 7.19 milliseconds. However, we really need 8.99 milliseconds because of all the check bits. Adding in the duration of the sector pulse before the read/write begins, the time for the sync word and the 250 us of preamble, you are up almost 9.4 ms out of the nominal 10 ms duration of a sector. The postamble at the nominal rotation speed would consist of almost 460 zeroes - around 638 milliseconds. 

SIMULATION RUN AND ALL TIMINGS AND BEHAVIORS VERIFIED

l completed a version that ignores the check bits written by the disk controller logic in the 1130 system. That seemed to grab the data properly. I then added an ECC testing circuit that would turn on a ECC_error latch during the write and leave it on until the next write begins. It will be routed out to the Fault indicator on the front panel. 

no hurricane damage at workshop and home

HURRICANE MILTON PASSED OVER US, THE CENTER ABOUT TEN MILES NORTH

My home had no water entering or other damage. The condo buildings had one palm tree knocked down, falling into an empty visitor's parking spot. Electricity and water remained on throughout the storm. It was less noisy inside than the hurricanes of two years ago. When the eye was overhead and everything got quiet, I was able to walk the dog. 

I drove to my workshop where I verified that not one drop of water entered under the regular or rolling door, the building was undamaged and the air conditioning remained on. This is good news, even if I did spend an hour lifting boxes of paper and other items from the floor to protect them from possible water damage, plus spreading covers over machinery and special documentation. 

Redesigned the sector and index pulse generator module - either uses real drive pulses or generates emulated pulses

GOAL OF MODIFICATION

I want a setting for the emulator where it can pass along the pulses from the physical 2310 drive in the IBM 1130, as well as operating without a drive by producing its own pulses. With a physical drive switched on, the disk arm will seek at the same time that the emulator virtually seeks. 

The disk controller logic in the IBM 1130 is wired to the physical 2310 drive, but the emulator is also tapped into the signals. Thus, when the controller tells the real disk arm to move forward one track, the emulator will see that and also advance the virtual track number itself. 

The disk controller sees the sector and index pulses, which it uses to determine when to turn on the read or write electronics of the physical drive. The emulator is passing along the physical drive's pulses so that both are in lock step. Thus when the controller sees it has entered the desired disk sector, it begins to read the clock and data lines from the physical drive (for a read) or controls the write data line when writing to the physical drive.

The heads are mechanically blocked from lowering onto the spinning disk surface of the physical drive. However, the controller is sent a signal that the heads have loaded and the drive becomes ready for access. 

As the write data line is modulated, the head is trying to record on the disk but it is very far above the platter and has no effect. The emulator is tapping this signal, however, capturing the bit pattern to write onto our virtual disk cartridge in the DRAM of the FPGA. 

As the drive enables the heads to sense the clock and data pulses from the spinning platter, no signal is detected since the head is too far above the surface. The emulator injects the signals into the line as if the disk head amplifier had read them, thus giving the 1130 and its disk controller the stream of bits it would have seen if using the physical disk in its traditional way. 

I set up a control signal, real_sectors, that tells this module whether to shadow the physical drive or to produce its own pulses. I might connect this to a switch on the RK-05 emulator or make it a configuration parameter. 

MADE CHANGES AND SIMULATED TO VERIFY OPERATION

The simulation shows perfectly shaped and timed pulses generated in both cases - real drive or emulated. My last remaining design task is to finish the sector write logic, where we capture the data being written from the 1130 to the drive. The emulator logic appears to correctly model the disk drive in all aspects. 

The top level module that ties together all the functional modules must be changed since we have different signals connected to a 2310 than to an RK-05. The various functional modules have changes in their input-output which have to be reflected and meshed together. 

The software in the Raspberry Pi needs updating to reflect our 2310 specific functionality. Too, I want to make use of the disk format files from simH versions of the IBM 1130, which likely differ from the RK-05 format files used by George Wiley's emulator. 

Seek logic simulated for 2310 emulation, modified version of George Wiley's RK-05 emulator

SEEK DIFFERENCES BETWEEN 2310 AND RK-05

The RK-05 seek interface sends a cylinder number and pulses a strobe signal, after which the drive either responds with an address accepted or an invalid address response signal. The timing for when the seek ends varies and another can be accepted is different from the 2310 as well. 

The 2310 seek interface sends a direction, a step size and pulses a go signal. The step is one or two tracks and direction is forward or reverse. The drive reports an access-ready signal and a home signal. Home informs the controller that the arm is at track 0, the outer edge of the disk platter. Access ready goes off 5 ms after the access go pulse is sent and turns back on 10 ms after that, to reflect the 14.6 ms max time for arm movement. 

Thus, the controller logic in the IBM 1130 will take a request for a relative movement of some number of tracks and convert it into multiple commands to the disk, using 1 and 2 track movements, until it is complete. If the arm reaches 0 and the command attempts to move in reverse, the arm remains at 0. Similarly, if the request for movement attempts to move the arm past 202, the last track, the arm remains at 202. 

The RK-05 emulator turns on an LED indicator called 'on cylinder' as part of its seek emulation. I decided to use that inversely, as a seek in process indicator. To convert the action to human timescale, my logic turns on the indicator for a quarter second after each seek action. Since the 2310 moves in bursts of 1 or 2 tracks, it will go on steady on longer movements. A full seek across the cartridge can be 1.5 seconds long, but a one to two track movement is 15ms and the LED will be on for 250ms. 

MODIFIED LOGIC AND SIMULATED SUCCESSFULLY

The logic is substantially different than for the RK-05. I simulated it with various conditions to verify both the behavior and the timing of every action. I was very pleased with the results and consider this part complete.