I chased down a hot bit in my design that was spuriously triggering memory cycles over and over. With the cause discovered and corrected, I could move on to debugging the USB read/write mechanism.
I brought out signals to the PMOD connectors and watched them on the logic analyzer to verify how my transactional FSM was dealing with the autoread/autowrite activity from the USB link. It was both good and bad news.
The good news is that I saw a reasonable sequence beginning with the Start signal, with or without the Read status line depending on the direction of transfer, and then the state machine wrapped up exchanging Done and Start.
The bad news was a flaw I spotted in the byte mode machine, which I corrected and then began to see that RAM was indeed storing and retrieving data. What I wrote came back properly.
I fired up the 'read sector' command and then read memory using the Adept utility. I was seeing the data although I think I have something backwards in how I am fetching RAM contents in word mode. I altered instrumentation as well as pored over my logic and the documentation. I am close, at least with the word mode retrieval.
Went to byte mode and did more testing. I am getting the data words out of memory, but the bottom half of the word comes before the top half. I have to look over all my signal assignments and verify whether this is the usual PC phenomenon of reversed bytes or if it is a flaw somewhere in my logic.
This turns out to be the expected order - it reads the low byte first (even address) then the high byte (next higher odd address). I tried the file transfer function of the Adept utility and got the same data that comes back in the autoread/autowrite mode.
The one issue is an off by one kind of error, in that the uploaded file is missing the first byte and everything else is shifted over by one. This is similar to the odd results I am getting reading via the autoread registers.
Since the actual storage of the deserialized words during a sector read is done as a word, it is not possible to drop half the word and shift things over. This tells me that my problem is in the USB autoread/write logic and addressing.
Each round of diagnostics takes 20+ minutes to synthesize and produce the bitstream, so that progress is steady but not speedy. Soon I will be out of energy for the evening.