Fighting to install the heads in the Diablo 31 drive

CHOSE THE REPAIRED HEADS BUT HAD TO CLEAN THEM 

The heads that my friend carefully polished to remove the head crash scratching actually looked good enough that I decided they would be the first set I try to fly. However, when examining them under the microscope I saw that the polishing powder was still on parts of the head. The bits of the powder are large enough that they would certainly cause a head crash as they flaked off during the vibration and airflow of disk operation. 

I could see it in the two round airholes that establish the cushion pressure as the head flies over the surface. I could see a lot more caked up behind the head, around the coil and on the attachment points. As I touched it with tools, it moved and came off in sludgy sections. 

I carefully removed as much as I could and bathed the heads in isopropyl alcohol in a container to try to wash away as much as I could. They seem pretty clean after all that work. 

HEADS STUBBORNLY REFUSING TO SLIDE FULLY INTO THE ARM

The heads should slide into the arm where clamps would be tightened to hold them down. They were not going in sufficiently. Unfortunately, the clamps are hidden inside the rotary motor and arm assembly, barely visible from the side using a light. I thus can't really see what is blocking the head from sliding into position. 

SEEING THE PROBLEM BY STUDYING THE PARTS CATALOG DRAWINGS

The excerpt from the parts drawing shows the three clamps and the slots on the right where the heads slide in (from the right moving inward to the left). It appears from the diagram that two of the clamps have a tang that should sit in a hole in the metal block. I have loosened them too much and they are now turning freely and not held in the proper alignment.

Once I get the two clamps tightened with the tang in the hole, I can loosen they slightly and they should remain in alignment. The third clamp should be oriented as shown but it freely spins round the bolt when there are no heads installed. I will then need to turn that to the proper vertical orientation before I attempt to slide the heads into the arm and get them to settle down between the clamps. 

I will attempt this on my next visit to the workshop. Once the heads are properly inserted and connected up, the drive should be ready for head alignment. The Diablo drive has a pushbutton inside that blocks the servo from moving the heads. I will hold that down and move the heads to a far cylinder manually then wait until the heads load. That way, any damage to the special CE cartridge used for alignment will be past the point I need to use. If the heads fly safely, I can move it back to cylinder 100 where the alignment data is written. 

Getting insight into what is happening during failure of 1130 MRAM doing reads - no more quantum effects

CURRENT SITUATION

When storing words of all 1 values (0xFFFF) into all of memory and then setting the machine to do continual storage reads looping through memory addresses, I will get sporadic parity errors where bit 2 fails to be set. Since the 1130 MRAM board has calculated parity based on that bits stored value of 1, the parity check fails and the machine stops.

I had been unable to see what was occurring because any time I put an oscilloscope probe or the logic analyzer on the incoming pin for setting the bit, the machine never failed. I finally dumped about over $500 into acquiring an active FET probe (used) which has less loading effect. 

MORE EXPERIMENTS WITH ACTIVE FET PROBE

I set the active probe to 10X attenuation and AC coupling, with a direct ground lead to the ground pin on the same SLT card as the incoming sense bit pulse. That worked as I wished - the rate of sporadic dropped bits didn't change thus my loading was not affecting the measured circuit. 

What I saw when a parity check was triggered was that the pulse which attempted to set the B register bit 2 was slightly different shaped than the others. It is there, but somehow it isn't flipping on the bit thus we get the parity check. 

The yellow trace is from the active FET probe recording a negative going pulse from my 1130 MRAM board which is intended to cause the SLT card to flip on the bit. Thousands prior to this successfully turned on the bit but this one didn't. I looked closer at the failed bit attempt as well as the successful one that came just before.

Pulse which fails to set the B register bit 2

Example of a pulse successfully setting the bit

The failed set involved a pulse that dropped about 2V whereas the successful ones show a pattern that comes from the capacitor discharging inside the SLT card and getting down to about .25V. The edge detector in SLT is a capacitor that is charged up through a resistor by an enable signal; then when the falling edge pulse arrives, it discharges the capacitor, resulting in the flipflop being turned on. 

The transistor on my 1130 MRAM board pulls the signal line down to ground. A pullup resistor on the SLT backplane causes the line to sit about +3V until the transistor fires to drop the line. We see the pin barely gets below 1V in the failing case but down to 0.25V when it succeeds. 

The transistor has a minimum beta of 25 and with a 1.6ma drive current it should be sinking over 40ma which should be sufficient for the activation of the IBM edge detector. The successful pulses reach a threshold of about 0.9V and then we see the capacitor delivering energy as it is discharged down to 0.25V. The failed pulse reaches about the same initial level but we don't see the capacitor delivering energy. 

I had a long, long chat with AI about what might be happening. Lots of speculation that didn't make sense, but I did 'listen' carefully and think about the phenomena being described. A good refresher on EE topics. Discussions about varying signals from other processing in the 1130 didn't make sense as this is a pure memory display loop.

As the AI pointed out, the SLT backplanes are designed for slow signals and higher frequencies such as from my board's fast pulse edge can ring across the backplane and cabling. The speculation was that ringing reflections could randomly cancel out my pulse edge if it arrives at just the wrong time However, the active FET probe is not showing any 'long term' ringing. 

When I started the discussion with the sporadic nature and failure rate of about 1 in 200,000 memory accesses, the AI asked me to look for a beat frequency of 1.388Hz but that is assuming it is always deterministically 1 in 200,000. Other suggestions assumed that the IBM flipflops are clocked, but they are really asynchronous circuits. Still, it did push me to think along many lines. Slight timing drift between my board generating the pulses and the clocks in the 1130 could line up bounce and dips on rails. 

I do remember seeing ground bounce in earlier versions of the board and that might still be an issue I need to address. I will add a braided ground strap from my board to the 1130 ground bus and see what effect that has. Another idea was to temporarily add a .1uF capacitor from ground to the -3V rail input of the SLT card and another .1uF capacitor between ground and the +6V rail input on the SLT card. This will absorb some high frequency bounce that might be caused by my fast pulse edges. 

The shape of the failed pulse looks to me as if the capacitor is not discharging. It has to be charged by the SLT circuit prior to my negative going pulse arriving. AI speculated that the resistors on the SLT cards have drifted high and are barely recharging the capacitor in time thus very random timing differences between memory cycles might eventually arrive just too soon to trigger. Bounce of the rail that charges the capacitor might also cause it to fail to charge sufficiently, it mused. 

This problem has bounced around the machine between the SLT cards. The B register is implemented across eight double width SLT cards, two bits per card. Previously the most common failure was bit 14, but recently it is bit 2. Thus it is unlikely that several cards have degraded to have exactly the same vulnerability. The only commonality I remember is that the errors always occurred on even numbered bits - those on row 3 of the SLT backplane. Thus cracked traces for power or ground could be a factor and only impact the cards that used that row. This may be coincidence however and the same issues might be possible on row 2 connections - odd bits. 

Bottom line, I can now see the failures where before they were masked by the loading of the probes. This should allow me to drill down to figure out what is causing my issues. I am making progress but don't yet have the smoking gun that pins down the exact cause. 

PLAN FOR NEXT OBSERVATIONS

When I next get to the workshop, I will add oscilloscope probes to the +6 and -3V pins of the SLT card and watch in AC mode for any activity on the rails that coincides with the failures. 

Started master file list from all 2315 cartridges and stored on Google workspace

ARCHIVED VIRTUAL DISKS FROM AN IBM 1130 SIMULATOR

I have been using the IBM 1130 simulator from Carlos Vincenzi and looked at the virtual disk drives from release 4.4.1.R9 as that is the version I have used the most. I grabbed 9 virtual disk drives from their and ran off the contents from the LET, FLET and SLET of each cartridge.

I entered them in the master spreadsheet I decided to use. This will let me quickly search for a file name and see all the cartridges that contain that file. It also provides an inventory of the cartridge as a whole. 

I will use the Unique field to assign some kind of globally unique identifier since I already have several virtual cartridges that had the same four hex digit ID assigned. For LET and FLET entries, it is the number of sectors the file consumes on disk. For the SLET entries, it shows the size in words of that phase. As well, the type field for the SLET will be the two character phase ID. 

Some files have multiple named entry points, thus the size and type fields are blank for the additional names. The names FADD, FSUB, FADDX and FSUBX are all contained in the one file whose initial entry is FADD. The file is in Disk System Format and takes up 8 sectors of the LET. 

In addition to the compact DSF format, files may be stored in Disk Core Image (DCI) format or in Disk Data Format (DDF). A DSF file must have all its linkages resolved and be combined with all other files it requires to produce the final core image that is what executes. Thus DSF is more compact, but DCI skips the time needed to link together all the files so it is faster to execute. DDF files are not executable. 

Files such as FADD are standard FORTRAN subroutines, loaded when the Fortran compiler was installed on this cartridge. Other files can be applications and utilities, either provided by IBM, from contributors or developed by the user. I will use the Purpose field to note what I discover about the files that are not standard parts of the Disk Monitor System and its compilers. 

The nine cartridges gave me 4, 095 entries in the spreadsheet. I envision the entire archive will be in the range of 100,000 to 200,000 entries. This is why I hosted it on Google. In addition, I can share it easily with other hobbyists and researchers. 

Work progressing on Diablo Archiver project

PYTHON APPLICATIONS DEVELOPED TO READ LISTINGS AND BUILD CSV FILE

I whipped up some Python code to open listing files - printer output of the IBM 1130 simulator running tasks to print the LET (Location Equivalency Table), FLET (Fixed Location Equivalency Table) and SLET (System Location Equivalency Table), extract all the file names along with some salient information, and create a comma separated values (CSV) file to add those to a spreadsheet in the format that I have initially defined. 

They ask for the Cartridge ID, the four hex characters that label the 2315 disk cartridge, a secondary name that I can maintain which is unique across all cartridge images, then read the printer file and spit out the CSV format file that can be used to import those values into a master spreadsheet recording the details of every file stored across all the archived cartridges. 

SOLDERED TOGETHER THE CONNECTOR ADAPTER BOARD

The Diablo came with a cable that has a Winchester MRAC-42 connector on one end and an IDC 40 pin connector on the other. The ribbon cable has a metal ground plane across its breadth, which supports signal integrity for the 37 signals thar are carried across the cable. 

I developed my Archiver PCB with an IDC 50 pin connector on a ribbon cable, supporting 25 signals with a ground wire between each signal wire. I whipped up a design for a board to connect those 25 signals to the corresponding pins of the IDC-40 connector on the Diablo cable. The board mounted one each IDC-40 and IDC-50 socket. 

WORKING ON THE CHALLENGE OF THE DIABLO POWER CONNECTOR

The rear of the Diablo drive has a male Winchester MRAC-14 connector, with five active pins that carry ground, +15V, -15V, another +15V and a second -15V power rail to operate the drive. The power supplies need a MRAC-14 socket. I don't have a cable for that.

MRAC connectors are fairly rare and have strong demand which forces high prices. The used sockets on eBay are all sold as plastic bodies without any metal contacts inside. The female contacts came in several types depending on the wire that would connect to it, whether by crimp or soldering. For my purposes I need the larger solder types.

The female contacts are sold in groups for several hundred dollars. Not a price I want to pay. At worst case I would have removed the male MRAC-14 connector and switched to a more readily available connector type for power. However, I did think I had found a solution that would come in  around $60 total. I found a female 9 pin connector that had the female contacts installed in the body, and I found a female 14 pin socket. Move the contacts, of which I only need 5, and viola.

However, when I received the 9 pin socket yesterday I realized that I had made a mistake. The Winchester connectors come in two flavors - MRA and MRAC - with the difference being that the MRA have the contacts permanently molded into the body, while the MRAC have contacts that can be removed and inserted. The contacts are not compatible between them, as the contacts for MRAC have a metal tab that locks them into the body.

What I had purchased was a MRA 9 pin socket with permanently molded contacts and a MRAC 14 pin body. I decided that I will find a way to re-use the contacts and put them into the 14 pin body. I spent a half hour carefully releasing the female contacts, although it required the destruction of the body. 

I will find a way to anchor the contacts into the 14 pin body. It might require epoxy or some other adhesive, but after I solder wires onto the contacts I will affix them to the body so that I have a workable power connector to hook to the Diablo.

SELECTING HEADS TO MOUNT IN THE DIABLO DRIVE

I pulled the heads from the Diablo drive (the two on the left in this picture) and collected a few heads I was assembling on compatible holders. I will decide which are the best and insert those into the Diablo drive.

Sent Head Adapter Tool off to fab; supports aligning heads in standard density Diablo 31 drive

GOOGLE AI CONTINUED TO SPEW INCORRECT INFORMATION

I asked Google AI to tell me the connector size for the head cable connection to the J10 PCB in the Diablo Disk drive. It responded authoritatively and confidently but embarrassingly incompetently. It was describing pin connections that made no sense. 

I called the software on one of the more egregious errors, claiming that each head had two erase coil windings. It apologized, said I was correct and updated its advice. Still woefully wrong. 

It asserted that the connection was two 6 pin connectors, one above the other. It still claimed that two leads came out from the erase coil and three leads for the read/write coil (two ends and a center tap Select line). Here is a picture of the cable from each head - only four pins just as is shown on the Diablo schematics. The erase coil has one end tied to the same Select line that is the center tap of the read/write coil, but the AI didn't grasp that. 

It said the connectors were standard 2.54mm pin headers. It gave pin numbers that don't match the Diablo schematics. The AI pinout had no ground connection and no mention of shields. 

I went to the workshop and examined the connector and the J10 PCB. I did some signal tracing as well. The connector is a standard 14 pin DIP socket. Not 6 on the top and 6 on the bottom. Further, it has four pins that grounding the shields of four tiny coaxial cables that carry the four head lines. 

I have tried using Google AI for some coding assists. It did a decent job giving me sample code to do new user interface tasks and using unfamiliar Python libraries. It seems to work adequately in that domain. However, for researching vintage computing hardware it emits AI slop. 

CORRECT PINOUT USED FOR MY DESIGN

I now know the pin assignments, which do match the pin numbers from the Diablo schematic of board J10. If you were to number a DIP socket in reverse, that is start with 1 at the top left, go to the right across the top row to 7, continue below with 8 and go back to the left bottom as pin 14, then the numbers match perfectly.

Pins 1, 2, 13 and 14 are connected to the board ground. Each pin on the connector has the shield of one of the four signal cables, two per head. Since there is no connection on the other end, there is no continuity to observe here but the PCB shows the pins tied to the ground plane. 

Pins 13 and 12 do nothing, they are unassigned. That leaves four pins each for the upper and lower heads. Each head has a connection to the common Select that ties the center tap of the read/write coil with one side of the erase coil. Each head has a line from the other side of the erase coil. There are two more lines, tied to the two ends of the center tapped read/write coil. 

4 - one side of the read/write coil that feeds Head Bus A

5 - the other side of the read/write coil, feeding Head Bus B

6 - Select, the common point

7 - the other end of the erase coil

8 - the other end of the erase coil on the second head

9 - Select for the second head

10 - one side of the read/write coil on second head, feeding Head Bus B

11 - other side of read/write coil, feeding Head Bus A

DESIGNED A SMALL PCB WITH A DIP 14 SOCKET AND DIP 14 MALE PINS

I whipped up a PCB that has pins to plug into the DIP-14 socket on the J10 PCB. It is marked with an up arrow much like the cable connector. Above that, it mounts a DIP-14 socket into which the head cable connector will plug. 

The erase coil of one head is connected to Head Bus A. The erase coil of the second head is connected to Head Bus B. The two Select lines for the heads are connected to their normal places. The other ends of the read/write coils are unconnected since this adapter uses the erase coil for alignment signal capture. 

SENT TO JLCPCB FAB FOR QUICK TURNAROUND

I expect the PCB to be built in two days and shipped back to me in about a week total time. It was fastest just to ship this off to JLCPCB who I had been using, in spite of the kind sponsorship from PCBWay.com since it adds time to arrange for them to pay for each sponsored PCB. 

Creating the Head Adapter Tool for aligning the Diablo drive

PROCESS IS DIFFERENT FOR STANDARD DENSITY (1130) CARTRIDGES

The method of aligning the heads takes advantage of the wider spacing of the poles of the erase coil in the head compared to the read/write coil. To do this, a special tool is connected between the J10 printed circuit board and the connector from the heads. It rewires the connections to switch the read preamplifiers from the ends of the read/write coil to the erase coil. 

This provides a very sharp null position over the track centerline so that only signals that are offset to the sides will be detected. The CE cartridge that is used to align packs had track 100 recorded with a special drive that offset the center of the spindle. 

This caused the written track to shift during a rotation, putting the center of the recorded track close to one edge and then the other of the .01" track width when it is read back on a drive with a normal spindle position. Since the center of the erase coil does not see a signal, the only signal picked up is from the portions of the special track that wander off center to be under one or the other pole of the erase coil. Correct alignment gives equal signal strength on both poles, otherwise we see more signal on one or the other so that the scope trace is unsymmetric. 

image for properly aligned head

High density machines, including the Diablo 31 we used to archive the Xerox PARC cartridges from the Alto computers, cannot use this method because the track width is too narrow. It must use the read/write coil for alignment. 

HEAD ADAPTER TOOL REWIRES THE CONNECTIONS TO USE THE ERASE COIL

No schematic or board view exists of this tool, but its purpose is described enough to work out a substitute. I will create a mini PCB that sits between the socket and the plug of the connector from the heads. It will also provide scoping connections.

Google AI gave me a start on the wiring, but it has several problems. As usual, it creates plausible text but can be way off on important details. The pin numbering from the AI output does NOT match any schematics of the Diablo drive. 

It refers at one point to the heads as having two erase and one read/write coil, which is NOT correct. It claims there are two erase coils (yes, but one per head) and a common return line (not true, separate wires from the heads only joined on the J10 PCB to form a common erase return path. 

Further, it doesn't seem to work with the method of selecting the head to align as described in the alignment procedure. The select line (a common line to all three coils in a head) has to be grounded. Grounding pin 5 of the J10 input pads selects the upper head; without that, the lower head is being selected. The wiring of the erase connections must conform with this. 

The AI discussion has both erase head ends connected across the differential amplifier, which is one for the top head and one for the bottom head. This could work if we have a floating select line hooked to one side of the erase coil in the head we aren't watching and an activated select line hooked to the other side of the coil on the head we care about. The two select lines go where the two erase return lines are connected on the original schematic. Here is what I think the wiring should be - from the head wires on the connector through to the socket on J10 PCB.

The normal wiring from the heads into J10 connects the two ends of both head's read/write coils together and they both feed the differential preamplifier, also called head bus A and head bus B. The erase coils are hooked on one end to the select line, as is the center tap of the read/write coils. The other end of the erase coil on each head comes onto J10 and are tied together there into a common erase return. 

All I need to do is disconnect the read/write coil ends and reroute the erase coil lines. Select lines remain unaffected. The erase coil line from one head goes to head bus A and the erase coil line of the other head is attached to head bus B. Very simple rerouting of the signals. 

HEAD SELECTION ON THE DIABLO DRIVE

The wiring of the heads uses a Select wire that is connected to the center tap of the read/write coils plus to one side of the erase coil. The two ends of the read/write coil are hooked to head bus A and B, while the other end of the erase coil is connected to a common return line that is grounded when erase current should flow through the erase coil. 

The select line is set to +14V when the write gate is turned on, thus the erase gate also drives the erase coil in this case. However, when the head is not selected, the select line is floating thus we don't have any erase or write current flow. For reading, the select line is set to 0.1V on the desired head and floats on the unselected head. 

As a result, even though the erase coils of both heads are connected to the differential preamplifier channels, only one select line is connected thus a signal voltage is only developed on one of the head bus channels at any time. 

WILL HAVE TO DETERMINE PIN NUMBERING OF ACTUAL CONNECTOR ON DRIVE

I have to sort out which pins lead to the read/write and erase coils of the two heads. The Diablo schematics should four pins per head, eight total. I know that it uses shielded cables to each head thus there are two more pins used for those shields. There is also mention of a chassis ground connection in the AI, but no documented in the Diablo manuals. That means I have 10 or 11 pins used in a 2x6 connector. If that matches what I find on the actual board and drive, then I can start developing the logic for the adapter.

I must work out how to connect the two erase coils (each with a return line) to the preamplifiers and how to cause only one to drive signals (selection of the head). I have to be convinced I have a rational wiring scheme before I design and manufacture my adapter board. 

Also to be determined is the pin spacing and size of the connector. I will have to put pins on my adapter board that slide into the J10 PCB with good contact, as well as mounting a compatible socket on my adapter where the connector from the disk heads will plug. Any elements needed to select which head I am aligning will also have to be placed on that board. A few turrets may be added to attach scope probes for raw measurements. 

Thinking about auto-aligning mechanism for the Diablo drive when archiving 2315 cartridges from an IBM 1130

IDEA FROM AI MAKES SENSE

I had listened to a hobbyist describing how they added a physical micro-positioner to offset a disk arm on a vintage drive when trying to archive content. It was for an entirely different disk drive and technology, but I was idly exploring the idea when I received a quite elegant solution from Google AI. 

It seems eminently achievable with minor modification to the Diablo drive and my FPGA archiver can generate the offset voltage to shift the heads forward and backward off the target track location. If a cartridge were written on a drive whose alignment of the heads was different from the standard position, then the recorded signals are slightly inward or outward from the standard track position by the amount of the misalignment. 

By modifying the servo feedback that keeps the heads exactly on position, the motor can shift the position where we read or write by some fraction of a track width. I can move to a particular track position with zero offset, then begin reading and interpreting the contents of the track at various offsets. The best results - no error checking or sync errors detected - would be the offset from which I archived the cartridge. 

HOW THE DISK DRIVE ARM MOVEMENT WORKS

The Diablo 31 disk drive uses a positioning mechanism that dynamically adjusts the position of the arm based on the target track and holds it in position based on an error signal it generates. Thus the drive moves the arms in and out driven by a rotary motor. This is very different from the IBM 13SD disk drive that is installed in an IBM 1130, which uses a mechanical ratchet to establish the arm at a particular track. The 13SD drive also uses a linear voice coil motor and only moves in 1 or 2 track increments, unlike the Diablo which can move smoothly as much as 203 tracks in one operation. 

A set of two signals 180 degrees out of phase are produced by teeth on a pickup disk that rotates under a fixed toothed transmitter on the motor. The signals A and B are used to create a sine wave that has a zero crossing at the spot where a track should be centered. The signals are also differentiated to judge velocity, so that the servo mechanism can control the speed of the arm movement as it seeks towards its target location. 

A counter is loaded with the number of tracks to be moved and is changed with every zero crossing of the position sine wave, until the count is complete. The drive then generates the error signal which is at zero when exactly aligned with the zero crossing point, but goes positive or negative when the arm moves out of position. This may occur from vibration, for example. 

The error signal is applied to the motor to bring it back to the zero crossing point, thus keeping the heads right over the center spot for the track. Whereas the 13SD drive mechanically locks the arm with the ratchet, the Diablo 31 has this servo loop to maintain position. 

ESSENCE OF THE MODIFICATION

The modification concept is very simple. Intercept the error signal and apply offset voltages to it, thus causing the servo to shift the head off center. An operational amplifier (OpAmp) is used to sum two voltages - the error signal from the drive electronics and an offset voltage in the range of -50mV to +50mV - which is then passed to the servo loop. 

If we shift the error signal by -20mV, for example, then the servo loop is going to move the arm until it has a true error signal of +20mV, which combines with our offset to yield a zero volt result that the servo locks into. We have a voltage source we can adjust via signals from the archiver, which generates the offset voltage. This feeds the new summing OpAmp in the servo loop.

The archiver normally produces 0V for the offset signal. In the adjustment mode, we pick a track to read and make multiple passes, each time varying the offset voltage in its range of -50mV to +50mV, picking the range of offsets that give us the best results. I envision a version of this that is used with an oscilloscope to visually judge the quality of the signal from the read head, as well as a pre-programmed version that attempts the assessment. 

An automated assessment might employ a phase locked loop on the clock bits and record cases where the clock is not detected at the proper time. That would be caused by the head voltage from the clock pulse dropping below the threshold for detection in the drive. Combine the 'missed clock' count with counts of check bit mismatch or sync failure and you would be able to mark those offset positions that are completely unsuitable. 

Looking over the counts on the range of offsets should yield the outer edges of acceptable reading for this test track. Find the midpoint and that is the desired offset with which to read for this side of the platter. Since the upper and lower heads are independently aligned, the correct offset may be different for the two sides. 

Then, during archiving operations after having determined the offsets, the archiver circuitry can produce the desired offset voltage appropriate for the head being selected. As the software switches between surfaces, the arm position could shift as well. 

We might need to add in some settling time when we change the offset. Thus, once the drive finishes a seek or a head selection change, when it believes it has stabilized the position and begins holding position with the servo loop, we apply the offset and wait a very short time. 

I don't think it requires much of a delay, since the dynamic nature of the servo loop which is keeping the arm in position already involves minute shifts to keep the head on the track, yet the drive design doesn't make any special compensation. It assumes this has no effect on quality of reading or writing. 

MY THOUGHTS ON IMPLEMENTING THIS

In my experience archiving around one hundred cartridges from the Xerox PARC library, I didn't find cartridges that had issues being read correctly due to misalignment. The issues we encountered were with cartridges whose surfaces already had some damage from light head crashes, which cascaded into heavier crashes that damaged the magnetic oxide to the point that the data wasn't recoverable in that area. 

The majority of the cartridges that I have on hand to archive came from two 1130 systems in Kansas, one at the business that owned my computer and another from a college nearby whose system was bought by the owner of my system as a second machine. At worst, I would have two alignments that between them would read everything but more likely all of the cartridges are recoverable with a single setting.

The IBM strategy with these drives was to align every drive to an IBM manufactured 'CE' cartridge, one that had a special pattern recorded to align heads. Each drive was aligned to these reference cartridges, which was intended to allow full interchangeability of cartridges between 1130 systems. 

The accuracy of alignment was not critical. The instructions for performing an alignment didn't enforce some maximum deviation from a perfect position. Following the instructions would likely result in heads that were offset from each other but were close enough for successful reading and interchange. 

The tracks are spaced .01 inches apart center to center (and the width of the recorded signal is then trimmed down by the erase head to a  width of .005"). This generates a dead band between tracks of approximately .003" which is where we would see the signal drop off. A full sine wave from the position detection circuitry would span .01" with the zero crossing point at the .005" center and the dead band appearing at around .0015" and ending around .0085" from the start of the sine wave. 

This suggests a simpler method of determining the offset for a head. Offset while watching a scope until the dead band appears, offset to the other side and note when the dead band appears, then pick the center of the range for the offset to use. This also appears to be a method where one could align a drive without having access to the special CE cartridge. If one arbitrarily assumes the cartridge one is currently reading is 'correct', then centering between the dead bands should give a workable alignment. 

The CE cartridge records a special pattern at track 100 that is an absolute reference. The above paragraph would be a relative reference, only as good as the alignment was for the cartridge you are using. 

Track 100 on the CE cartridge was recorded with the axis of rotation offset so that the track circle is offset from the center. Thus, the recorded signal will shift inward and outward from the arm position during each rotation. Watching on a scope, the arm is shifted in or out until the size of the signal is the same on both sides of the head, meaning it spends equal time on each side. That would put the head directly over the desired absolute track position. 

Pattern when 80% off from good alignment

Pattern when only 40% off

Pattern when correctly aligned