Finished checking and fixing up the diagnostic load file

FOUND ALL THE DIFFERENCES TO THE LISTING

I ended up with quite a few words that didn't match, although most of them are consistently different because of some corrupted test sequences towards the end of the code. Since the test sequences were a bit longer the address of data at the end of the program shifted, thus any instructions that referenced these locations did not agree with the listing. 

In addition to all the differences based on the shifted locations near the end, there was a single word that was incorrect - the value that caused our spurious error message. However, it was not just a matter of shifted locations for everything else. Some of the test sequences to be typed were alternatives to the code I discovered but seemed like it would accomplish the same purpose.

ALTERNATIVE TYPING SEQUENCES

The first deviations in test sequences began in the middle of the Backspace and Index test. This test begins by issuing a tab, then types backspace in reverse backing up from the tab column, then does a tab and types index with a line feed and backspace between each character so that it appears vertically on the page. 

The code I have in the file issues a character code that combines more than one control function in the same character, which isn't defined as valid in the programming documentation. Every control function has the low order bit set to 1. The other bits define which control function:

• 81 - carriage return
• 41 - tab
• 21 - space
• 11 - backspace
• 09 - shift to black
• 05 - shift to red
• 03 - line feed

Note that the functions above are a single bit set plus the low order one. My listing for the diagnostic accomplishes the index part of the Backspace and Index test by issuing an 11 then an 03, to backspace then linefeed. The load file has a single control character 13, which seems to combine the backspace and the line feed into a single command. 

Because the load file combines these commands, it is shorter by three words. That displaces all the sequences that follow (Auto Carrier Return, Rock, Roll and Twist) plus all the data and code that follows the sequences. One word was added to a data table, which consumes one of the three words that was gained by compressing pairs of movement commands into a single hybrid command such as line feed plus backspace. 

CORRECTED LOAD FILE FOR SINGLE CORRUPTED WORD

Since the typing sequences and related address shifting appear to be an intentional update made by IBM in order to fit a change in the same diagnostic test footprint, the only difference that seemed to matter was the constant for the desired Device Status Word (DSW). After the typewriter is commanded to type a character with an XIO Write instruction, while the mechanical operation is underway but before it completes. an XIO Sense Device should return a DSW that has both the busy and not ready bits set. The constant should have had both bits turned on, but it instead only had a bit for busy status. 

NEXT STEPS

With the file corrected, when I next arrive at the workshop I should be able to run the diagnostic without receiving the false error messages that were caused by the corrupted constant. I have some things to do that will delay my next visit to the shop, but once I am able to return I will load the fixed file and try out the typewriter.

I do have questions about the unorthodox combination commands that mix more than one movement command in the same XIO Write instruction. The reason I want to look closer is because the controller logic is sensitive to two feedback signals coming from the typewriter, which are -Twr CB Response and +Twr CrLfT Interlock, both of which are produced by multiple microswitches. 

Two of the typewriter movements, tab and carrier return, are variable duration events which depend upon pairs of microswitches to properly cover the entire duration. If the adjustments aren't correct, we could see a spurious edge on the signal that convinces the controller logic that the movement is complete even though the signal goes back to busy for additional time. 

I will put the oscilloscope on the two feedback signals and watch what occurs with the combination movement commands, hand coding an XIO Write to trigger the movement. If anything looks wonky, I will know the microswitch(es) to check and readjust. 

More on the errors with the console printer (typewriter) diagnostic

USED SCOPE TO VERIFY THAT NOT READY AND BUSY ARE PRESENT

I could clearly see that when an XIO Write was issued to the typewriter, both Busy and Not Ready activated at the same time and for the appropriate duration. I traced the Not Ready signal to every location in the machine just to satisfy myself there was no issue with the DSW. 

RAN DIAGNOSTIC AGAIN, THE SAVED DSW WAS CORRECT BUT ERROR PRINTED

Indeed, after an XIO Sense Device the Accumulator (ACC) had bits 3, 4 and 5 set, which stand for Console/KB switch set to Console, typewriter busy, and typewriter not ready, respectively. This is correct. 

The diagnostic printed error E0402 which indicated that our status was not correct. The text in the documentation suggests that the busy status was wrong, but it was just poorly worded. Nor was the Not Ready status wrong - as we just verified. The error message should not have been printed. 

STEPPING THROUGH TESTING CODE, I FOUND A CONSTANT WAS INCORRECT

The code involved in this producing this error message had immediately issued an XIO Sense Device after it did an XIO Write to type a character. I saw it apply some bit manipulation then check to see that the saved DSW matched the archetype for a correct status. However, the word with the archetype status, which should have held x0C00, was instead 0x0800. This was triggering the spurious error message. 

I did a quick update of that word to the proper value, reran the diagnostic and, miracle of miracles, the error message was no longer emitted. However, if there was one corrupted value, there may be more. 

COMPARING DIAGNOSTIC ASSEMBLY LISTING AGAINST CORE FILE

I began to check the value of each word in the file I load into core to run the diagnostic, comparing it to the printed listing of the diagnostic program. This is time consuming. So far, I have found the one error word that caused the erroneous error message, but also see that the address of one routine near the end of the listing is off by two words. However, every other word so far has matched perfectly. 

As I finish the cross check, I can clean up my diagnostic program file so that it will be loaded exactly as intended by the authors at IBM and therefore should run flawlessly. 

Substitute relay arrived for 2501 card reader, tested and installed

RELAY R3 HAD AN OPEN COIL THUS REPLACEMENT NEEDED

The power supply box includes a function to keep the main motor of the card reader running for 15 seconds after the 2501 receives its last read or feed request via an -execute command signal. Relay R3 latches every time -execute command arrives but the voltage across the coil declines based on an RC circuit until about 15 seconds have elapsed, when the relay coil is no longer able to hold the connection. 

The contacts of relay R3 send a signal -motor hold sw back to the 1130 system's controller logic, which uses it to maintain or drop the -motor relay command back to the reader. If this isn't working, the motor will shut off instantly after every card is read, which is hard on the motor and disruptive to the process of reading. 

EXACT PART NOT AVAILABLE BUT LOCATED A RELAY THAT SHOULD WORK PROPERLY

The Sigma part number did not come up in any online search, but there were many similar relays from Sigma that I could choose from. I looked for the critical specifications to get as close to the original relay as possible. This included the voltage and current rating of the contacts, the voltage for the coil, the DC resistance of the coil and factors like the drop out voltage. 

The original relay had contacts rated for 2A of current, but that is extremely far above the actual signal currents used in the 2501 and 1130 system. Thus, a 1A part was very suitable. The voltages for the contact, coil, and coil drop out were identical. The resistance of the original relay was 10K but the part I found was 9K. 

The final difference was the mounting method - the hole locations and shape of the mounting foot. I will have to adjust for the difference to install this new relay into the power supply box. 

CONNECTED AND TESTED ON THE WORKBENCH

I connected the power supply box to my 220V step up transformer and used some resistors and jumpers to simulate the control signal -execute command to trigger R3. My VOM was hooked across the contacts of the new relay to let me hear the duration of the relay actuation. The circuitry around the relay includes a potentiometer where I can fine tune the time duration, which should help me compensate for any differences due to the substitute relay.

The relay activated cleanly when the control signal was given. The relay opened up after 5.5 seconds. Based on that, I began adjusting the potentiometer but the max delay I could achieve was around 7 seconds. 

I experimented changing the resistance of the time adjustment leg - the potentiometer plus a 10K resistor - to see if I could lengthen the hold. Even with an infinite resistance, the relay held for 13 to 16 seconds, varying a bit, which I deemed close enough to proceed. The specification for motor hold time is 15 seconds +/- 3, therefore we are within the proper range. 

The potentiometer and related resistor are out of the circuit. The relay coil appears to be draining power faster than the original did, or it has a higher drop out voltage, or both. An alternative solution would be a larger capacitor in the timing circuit, which would accommodate the higher current flow and lower its voltage at a slower rate. However, since the unit performs adequately now, I won't pursue this alternative.

MODIFIED MOUNTING METHOD TO INSTALL INTO POWER SUPPLY BOX

The original relay had a rectangular plate on the back with holes near the top and bottom. The new relay has a different shape and hole pattern, thus I had to take off the plate from the old relay, drill out a hole and use a screw to attach the new relay to the plate. 

READY TO PUT POWER SUPPLY BOX BACK INTO 2501 CARD READER

The lower compartment of the 2501 card reader holds the power supply box, a card cage for the SLT circuits and the connectors used to connect cables to the 1130 system. The power supply box fits in the compartment using slots in the box that match mounting hardware in the 2501.

A flat rail runs across the top of the compartment, from front to back. Slots in the top of the power supply box allow it to fit over the rail, with enough room in the slot to move further upward than its final mounting position. 

That permits the bottom of the power supply box to be swung over the top of a rectangular rail that sits across the bottom of the compartment, running from front to back. Square cutouts on the bottom of the power supply box allow the box to settle down onto the rail. This suspends the box from moving side to side in the 2501. A bolt goes through the bottom of the power supply box to lock it down in position on the bottom of the 2501 compartment. 

Once I do this I will be reconnecting all the cables and wires I had to disconnect in order to move the power supply box to the bench for testing and repair. 

Oops - error in test code thus troubleshooting the wrong problem

MY HAND CODE TO TEST THE DSW AND SAVE IT WAS DEFECTIVE

The error messages from the diagnostic were described as indicating the failure of the typewriter to appear busy during an output operation. The hand code was intended to save the Device Status Word (DSW) immediately after a character was output, with the result saved matching the character code of the letter I typed rather than a valid status.

Based on that I was down a rabbit hole trying to imagine a failure scenario that would place the character code in the accumulator register (ACC) after a sense DSW. It was quite unlikely which meant that I didn't have a good starting point to test signals to eventually locate a fault. 

Imagine my embarrassment when I began to execute the code in single cycle mode to see exactly how the XIO Sense Device was working. I noticed that I was saving the ACC at the wrong time, just after I typed the letter with XIO Write, not after the XIO Sense Device. Thus the value I saved was in fact reasonable and consistent. Unfortunately, it was not an indication of what might be wrong in the diagnostic!

ACTUAL ERROR DISCOVERED BY LOOKING AT DIAGNOSTIC MEMORY LOCATIONS

I pulled out the listing of the diagnostic program and found the point where it was writing the error message. The code showed me a location where the DSW had been saved before it was checked doing an exclusive OR with the value x0C00 and requiring the result to be all zeroes. Those two bits in the DSW are busy and not ready, respectively. 

The busy bit was on, as it should. The not ready bit was not set. My DSW was x0800 but had to match x0C00 for the test to pass.

NOT READY SHOULD GO ON AT THE SAME TIME AS BUSY

The architecture of the IBM 1130 specifies that the not ready bit is turned on by multiple things, one of which is a busy condition. It is also set when the typewriter is out of paper (Forms Check lamp is lit on the 1130 console). In the past this had worked properly, so the diagnostic error was new, popping up sometime while I was doing the last round of typewriter adjustments. 

Since it had occurred immediately after I changed things on the typewriter device, the likely cause was something wrong in the typewriter itself. Once I watched the typewriter perform properly I turned my attention to the typewriter controller logic inside the IBM 1130. Sadly I read the error as indicating that the busy bit was not turning on. This bit turns off once the operation is complete and the controller logic requests an interrupt from the processor. 

I then set up a defective program to look at the DSW to check for busy right after the XIO Write but before the interrupt was requested. Based on a flawed test, I was chasing a false error scenario in the controller logic. Armed with the actual situation that triggers the error message in the diagnostic, I can start testing the portion of the 1130 that is involved. 

NOT READY STATUS LOGIC

There is a small amount of logic and connections involved in turning on not ready while the typewriter is busy. This all begins when the typewriter turns on its busy flipflop, during the XIO Write instruction, step E1, at clock time T6. That signal stays on until the rising edge of the -Twr CB Response signal from the typewriter. 

At this time, the busy flipflop is turned off and the operation complete flipflop is turned on. The request for an interrupt on level 4 is raised whenever operation complete is set. A subsequent XIO Sense Device with bit 15 set will clear the operation complete flipflop, stopping the request for an interrupt. This normally is issued within the interrupt request handler code so that when the interrupt handler exits, we don't immediately jump back in due to the active request. 

-Twr CB Response is created by a chain of microswitches in the typewriter, all of which are normally closed. When one or more of them opens, indicating that a mechanical operation is in a sensitive portion of its cycle, the signal drops to logic 0. Once that protected portion of a cycle is finished the switch closes again, creating the rising edge back to logic 1 state. 

Since we are receiving the interrupt request we know that the rising edge is detected. We know from looking at the DSW after the interrupt that the busy bit is not on. I know from the stored DSW in the diagnostic that the busy bit was set while the typewriter was outputting the chosen character. 

The signal -Twr Not Ready is generated by the logic below:

As you can see, it is very simple. On the left, the End of Forms microswitch is debounced and is an inverted logic signal -Twr End of Forms. The -Twr Busy signal is also inverted. 

If both of them are logic high, thus we are not busy and we don't have an end of forms, then the signal +Twr Not Ready is generated as logic low due to the rules of a NAND gate. If either condition is true (logic low) then we raise the +Twr Not Ready signal that goes over to produce the DSW bit 4. 

Also, if we have a logic high on this generated +Twr Not Ready signal and at the same time we are not busy (logic high on -Twr Busy) then we drive the -Twr Forms Check Lamp line low to light the bulb. This means that the lamp doesn't actually go on while we are performing a typewriter mechanical operation, waiting until the completion. 

For example, if the carrier is near the right margin and a carrier return is requested, when the platen rolls up one line, we might have the paper end leave the End of Forms microswitch. The lamp doesn't turn on until the carrier has finished its move to the left margin. Presumably an eagle eye could spot that sequence of operations, but it seems to be a unnecessarily sophisticated implementation of a warning lamp. 

Finally the signal -Twr Busy that we are combining to produce the -Twr Not Ready condition comes from this logic:

The Twr Cycle flipflop is turned on by the combination of XIO Write, Area 1 (typewriter address) and time T6, as long as the typewriter is not busy. The busy signal arms the edge detector which fires off a set pulse when we exit T6 in an XIO Write to the typewriter. The flipflop is turned off when the signal +Twr Interlock Latch drops as long as we are not in a shift cycle, since shift cycle conditions the edge trigger. 

When the typewriter needs to shift between the upper case and lower case hemispheres of the typeball, it converts the request into a sequence of two typewriter actions. First, a shift is fired off. When that is complete, we then fire off the character type command. 

The interlock latch is on while mechanical action is underway and will turn off after the shift and again after the typing of a character. We don't want to turn off the print cycle after the shift, only when the actual typing is done. 

Our busy condition is formed with a NAND gate, turning on if any of three signals are true:

• Twr cycle flipflop is set
• We detected the end of line microswitch on the typewriter
• The interlock latch is on due to mechanical motion

Since this output is an inverted logic signal, -Twr Busy, it is logic low when on. That feeds directly to the logic producing the +Twr Not Ready signal (see diagram). 

Now that we see how the two signals, -Twr Busy and +Twr Not Ready, are produced, we look at the logic which presents +Twr Not Ready as bit 5 of the DSW.

When we have an XIO Sense Device for Area 1 and the +Twr Not Ready signal all at logic high, we set DSW bit 5 low (which produces a 1 in the DSW). 

All of the logic involved is on gate A, compartment C1 of the 1130, which eliminates any compartment to compartment cables from suspicion. We have just a few gates that might be malfunctioning. The only other possibility is a broken trace on the backplane of compartment C1, which is very unlikely. 

Potential bad gates include:

• A C1 C2 D07 output producing the -DSW Bit 5
• A C1 E5 D04 producing +Twr Not Ready

The correct operation of the logic producing the interrupt request and good status for busy eliminates any other gates in the machine from consideration. 

OSCILLOSCOPE PROBE OF HAND CODE TO WATCH NOT READY SIGNAL

This is a very simple test - trigger the scope when the busy condition is produced at A C1 D4 D04, on the falling edge. Watch the two signals above to see if they are generated appropriately. Based on that, test the gate in question, find the bad component and then fix it. 

Debugging issue with XIO Sense DSW - part 2

GATING ONE REGISTER TO ANOTHER IS A BIT COMPLICATED

The terminology suggests that you will get an exact copy of the source register in the destination register, but the reality of the circuitry is important to understand. Gating into a register involves IBM's edge sensitive gates, which produce a pulse to set a flipflop for the bit. This pulse sets the flipflop. It does not reset it. The contents of the source will not be turning off the flipflop of the destination. 

Further, the control signal that arms the edge sensitive gate is the bit value of the source. If the source holds a 0 value, then the edge sensitive gate is NOT armed and cannot set the flipflip. It is when the source holds a 1 value that the gate is armed and turns on the flipflop at the appropriate time. We transfer 1 values but not 0 values. 

This may sound like a quibble, but it means the entirely different circuits are involved in resetting the bits of the destination. This would be a register clear signal that turns all the flipflops to 0. Now imagine that the register previously held a value of x3C00 and it was not cleared. If the source holds 0x0800 when the gating occurs, the destination register remains at x3C00. If the source holds x00F0 then the destination register would become x3CF0. We are doing an OR into the destination, so that we absolutely must have it cleared to x0000 before we do the gating. 

ONE POTENTIAL FAILURE MECHANISM

If we first posit that a register has the typed character code at the end of the XIO Write instruction, and that nothing in the execution of the I1 and E1 steps of the XIO Sense DSW make use of that hypothetical register, then if the register clearing pulse does not get to the register, we might get the symptoms I observe where any bits from the typed character code remain on in the destination register. 

REVIEWING PATH OF DSW DATA FROM CONTROLLER TO ACCUMULATOR REGISTER

During execution of an XIO Sense DSW, at the start of the E2 step of execution, the typewriter controller logic turns on bits that should be a 1 in the DSW. It does not turn off any bits - again, the circuits in the 1130 generally are asymmetrical and flip bits on with edge sensitive gates. While the controller holds the desired bits at 1, pulling them to logic low since the IO Bus is inverted, an early step of E2 for the instruction gates the IO Bus to the B Bus. Assuming the B bus was cleared previously then it has 1 bits only in the positions that were set in the IO Bus.

A bit later in the E2 step of the instruction, it gates data from the B register to the D register. If the D register was previously cleared then it will match the B register value. A touch after the transfer, control lines are set to the arithmetic logical unit to cause the value in the D register to be transferred into the A (Accumulator) register. 

TRYING TO FIND A FAILURE MECHANISM THAT INVOLVES THE D REGISTER

We know that the B register updated after every memory access, so that the original typed character code from the XIO Write instruction is replaced, first by the XIO Sense DSW instruction itself, then by word 2 of the IOCC in step E1, and finally from gating of the IO Bus in step E2. 

However, fetching instructions and reading the IOCC does not involve the D and A registers, only the B register. Thus there is the potential that something has gone wrong with clearing one or both of them, so that when the IO Bus is gated into D we are just doing an OR of the IO bus with the prior contents of D. 

For this to happen, we must have the character code of the XIO Write instruction somehow get transferred to the D register. There is no need for this to happen as the XIO Write should simply have the data in the B register so the typewriter controller can work with. I must find evidence that a transfer takes place to D otherwise this explanation of the defect can't be correct. 

Looking at the logic of the machine, the data should stop at the B register because the CCC counter is decremented to 0 at the start of step E3 of the XIO Write instruction. The last thing in the D and A registers will be the first word of the IOCC as it was read in step E2. For this speculation to cause the symptoms we see, the transfer into D must happen in E3 of the XIO Write, through some kind of defect. Then, a second defect must suppress the clearing of register D so that when the XIO Sense DSW step E2 gates in the IO Bus, we get an OR with the prior contents of D.

I am skeptical that I would have two scattered defects that combine in this way but otherwise code seems to run fine on the 1130 system. I need a starting hypothesis to debug the machine, otherwise I might need to monitor hundreds of signals blindly to try to spot a problem. More thought is required. 

Debugging issue with XIO Sense DSW - part 1

BACKGROUND FOR UNDERSTANDING THE SENSE DSW ISSUE

The 1130 has a common input bus for I/O data as well as the device status words, with all the sources for a bit tied together so that any one of them can pull the line to ground to indicate a 1 value. This means that many circuits can be turning on those bits. 

When reading from a peripheral, the IO bus is gated into the B bus (memory data register or storage buffer register) at the correct time so that it is written back to the current memory word. DSW status bits are also gated to the B register in the same way. 

This means that the issue could also be occurring in the B register, but the IO bus value was correct. That is another avenue to chase down. In addition, there are other registers involved, which I will discuss below. 

The 1130 is a memory centric machine, with instruction execution involving one or more memory access cycles. An address is placed in the M register (Storage Address Register) before the cycle begins and the contents of memory are placed into the B register (Storage Data Register) in the midst of the cycle. If a new value is to be written into that memory location, the B register is changed before the second half of the storage cycle takes place.

The instructions themselves are in memory, thus before they can execute they must be read with a storage access. Each memory/storage access cycle is one of a number of defined types. I1 is what fetches the first word of an instruction, but we could need an additional storage cycle I2 if it is a doubleword instruction. 

The address of the target of the instruction must be determined and these might require storage access cycles themselves - IA for indirect addresses and IX if an index register is involved since those reside in memory at fixed addresses. 

Once all the preparation steps, at a minimum I1 but as much as four cycles I1, I2, IX and IA, then the purpose of the instruction can be satisfied by execution memory cycles. E1 is the first execution memory cycle, where a value might be fetched from memory or placed in memory. Some instructions may not access the memory, instead changing arithmetic or logical data, but that occurs using a storage cycle but setting a signal that suppresses access to the core memory during the cycle. 

We see the I register (Instruction Address Register) is moved into the M register before a cycle to cause the instruction's first word to be read into the B register. In the diagram above, a simple instruction has only the I1 cycle and then the E1 cycle to grab the value in the target memory location and place it in the B register. 

In the 1130, every memory access produces a value in the B register. When executing the XIO Write instruction, the last memory location we read is the address where the character we want to print is stored, thus B contains that value. When it then starts to execute the XIO Sense DSW (step I1), the first memory address read is the instruction word, which replaces the B register. The XIO step E1 then fetches the second word of the Input Output Control Command (IOCC) which has the device, IO function and sometimes control bits. Thus word 2 of the IOCC is in the B register. 

In step E2, the XIO fetches the first word of the IOCC which often is an address but for XIO Sense DSW the storage read is blocked and we instead just gate the IO bus to B register. The XIO Write, step E3, on the other hand, will fetch memory at the address we just picked up. For an XIO Sense Device, the value in the B register is then gated to the D (Arithmetic Factor Register AFR) and passed through to the A (Accumulator) register using a couple of arithmetic logical unit control signals. 

Somehow the value in the B register looks more like an XIO Write than an XIO Sense Device. However, the first word of the IOCC I used was not the address where the character value was stored, so it could NOT be actually reading it from memory like an XIO Write E3. 

The data that was in the B register multiple memory fetches ago is now showing up in the A register during the XIO Sense DSW step E2. While it looks as if the IO bus for the sense DSW stored the 'saved' value in B, it had no path to make that transfer happen. I think instead this has to do with the D and A registers. They would not be disturbed by the I1 and E1 stages of the XIO Sense DSW instruction execution, thus anything in them would remain there. 

The problem with this hypothesis is that the XIO Write should NOT be transferring the B register value to D or A. In order for the observed actions to take place, the XIO Write would have to transfer the B reg value somewhere else, which it shouldn't, then the XIO Sense Device would have to move something other than the IO bus value to B, D and A. 

Compare the XIO Write instruction, which is diagrammed above, with the XIO Sense DSW instruction diagrammed below. 

The E1 step of XIO Write will grab the second word of the IOCC and store it in the U register to determine which device and XIO function is being performed. The next storage cycle, E2, will grab the first word of the IOCC which contains the address in memory where the character data for typing is stored. That address moves to the M register and the E3 storage cycle causes the character value to be fetched into the B register. The typewriter controller logic looks at the value in the B register to determine how to control the typewriter. 

The E1 step of XIO Sense DSW also grabs word two of the IOCC, and another storage cycle takes place as E2. However, the storage access is blocked, nothing goes in or out of core memory. Instead, the typewriter controller logic sets bits to 1 in the IO bus and it is gated to move into the B register. Other signals than gate the movement of the B register to the D register (Arithmetic Factor Register) and control signals cause the value in D to move into the A register (Accumulator). All those gated moves happen during a storage cycle but no actual memory access occurs during that time. 

The address in the first word of the IOCC for XIO Sense DSW may be moved to the M register but it is ignored since we have inhibited memory access. The typewriter controller logic is only able to set some status bits in the IO bus. It is not able to write back the entire character value. This is the root of the problem - A register ends up with a value that is long since gone from the B register when XIO Sense DSW starts executing and the controller logic has no way to write it back even if it had it. 

IBM 1130 typewriter (console printer) repair and adjustment - part 10

USING SCOPE TO VERIFY BUSY CONDITION FROM TYPEWRITER

I could clearly see the -Twr CB Response signal drop during the typing of each character, although the console printer diagnostic as reporting that the DSW did not show the typewriter busy when it was sensed immediately after an XIO Write was executed. 

There could be a failure in the controller logic inside the 1130 system that is failing to indicate the busy condition. This is set when the XIO Write instruction is completing and cleared by the -Twr CB Response signal having gone low for a while and then returning to high. When the signal returns to high, besides turning off the busy signal it also requests an interrupt on IL4, presenting Operation Complete status.  

HAND CODE TO ISSUE XIO WRITE AND XIO SENSE DSW IMMEDIATELY AFTER

I set up the machine so that when the interrupt arrives on IL4 when the typing completes, the machine simply waits. Then, the code that fires off the character typing has a sense DSW immediately, stores it in a chosen memory location and at the end waits.

I could see that the Accumulator, as well as the chosen memory location, contained x3C00 which is not correct for what should be happening. This is why the diagnostic complained. I was suspicious because the value happened to match the character I asked to type - x3C is an A - so I altered the character I was typing to J (x7C) and that value was now returned for the  Sense DSW.

This should NOT happen.  This is not a typewriter issue, so I will blog about this under a new title and once it is resolved I can go back to documenting the console printer repair and adjustment.