Deconstructing the +6V regulator SMS card schematic to isolate functions

DIGIKEY IS SLOW TO FILL MY PARTS ORDER DUE TO HEAVY VOLUME

As the parts have not yet been shipped, they will not arrive by midweek as I had expected. I took the time to document the regulator and explain some of its function.

REGULATOR HAS AN SMS CARD TO REGULATE THE VOLTAGE PLUS OTHER PARTS

The regulator has six IBM type 108 germanium power transistors each on a large heat sink, a circuit breaker, a few other parts and then two SMS cards. One card simply detects when the output voltage is above a trigger threshold, so that it can short the output to cause the circuit breaker to trip. The other is the logic that drives the six power transistors so that the current they are passing will produce a 6V voltage drop over the load. 

The schematic for the regulator includes all the above parts. In addition, it is drawn with the IBM conventions where they show electron flow from the top to the bottom, upside down from the usual orientation in drawing circuits that considers current to flow from positive to negative. IBM also draws transistors in a non-standard way. 

DIFFERENTIAL/COMPARATOR PORTION OF THE CIRCUIT

The two transistors above have their emitters connected through an emitter resistor. This biases the voltage needed on the base of the transistor to cause it to conduct - the more current through the pair of transistors, the higher the voltage drop on R5 which means that the base needs to be more negative to enter the conduction region. 

The right transistor feeds a bias current to the power transistor driver, based on the voltage seen across the output terminals of the regulator. It is trimmed by a potentiometer to produce the 6V voltage drop on the load. The left transistor drives the amplifier based on a fixed voltage from a Zener diode.

If the voltage across the output dips below 6V, the right transistor has less current flow or cuts off, lowering the total current through the emitter resistor R5. This causes the left transistor to conduct more heavily. The left transistor current is amplified and drives the power transistors to increase current leading to restoration of the output voltage. 

If the voltage across the load bumps over 6V, the right transistor conducts more heavily, which increases the emitter resistor R5 voltage drop. That lowers the conduction of the left transistor, the amplifier has a lower output and therefore the power transistors lower the current to the load until the voltage drop restores to 6V. 

AMPLIFIER PORTION OF THE CIRCUIT

The differential circuit left transistor output current is fed into the base of transistor T3. As the differential circuit requests more power, transistor T3 conducts more heavily. Its output feeds the base of transistor T4, adding further gain. T4 delivers more current from the - input rail to the base of transistor T6, again being amplified to pass current from the - rail to the bases of the six power transistors. 

POWER PORTION OF THE CIRCUIT

Six IBM type 108 transistors operate in parallel to deliver the current requirements of this regulator. It is capable of delivering 24A across the load. The transistors have emitter resistors that cause these to balance the load across the six. As a transistor delivers more current, the voltage drop on its emitter resistor rises so that the voltage difference at the base lowers to decrease conduction. 

OVERVOLTAGE PROTECTION CARD

A differential pair of transistors T2 and T3 compare the fixed voltage of a Zener diode on the left with a fraction of the actual output voltage delivered to the right transistor through an adjustable potentiometer. When the voltage on the right transistor gets high enough, the right transistor conducts enough to reach the trigger voltage level for the silicon controlled rectifier (SCR) SCR4. Once triggered the SCR stays in conduction until power is removed. As SCR4 conducts, it delivers the trigger voltage to SCR46, which shorts the entire output of the regulator. 

This circuit will force the circuit breaker to trip on the regulator. It fires in a few tens of microseconds, protecting the logic components in the 1130 from damage if the voltage is too high. The potentiometer is set to a protective target, e.g. 6.8V, where the card will cut off the output voltage. 

Further dive into the 6V regulator circuit breaker spurious tripping

SET SCOPE TO TRIGGER IF REGULATOR OUTPUT HITS 6.7 OR HIGHER

I hooked the oscilloscope up to the 6V output of the regulator and set the trigger to a level of 6.7V so that I would see whether a high level is the cause of the spurious tripping of the circuit breaker. The overvoltage protection card will trip in a few tens of microseconds if the voltage is above the 6.8V trigger level I had set. 

The system tripped immediately, so I isolated the logic from the regulator and then watched the voltage on the output without the overvoltage protection card installed. It zoomed up to 15V and stayed there. I pulled the regulator card out and found a solder bridge defect where I had removed and replaced a couple of parts. After removing the solder bridge, the regulator worked properly and generated 6V. I hooked the logic back up.

The observed voltage completely dashes the theory that the breaker is tripping due to an overvoltage condition detected by the overvoltage protection card which clamps the output to zero. What I am seeing instead is that when I power down for a short interval and then power back up, the voltage comes up to about 3V and oscillates around that level, leading to excessive current draw which trips the breaker.

POTENTIAL CAUSES

It is possible that some parts out in the 1130 logic are producing a short circuit under the repower conditions I am seeing, causing the 24A capacity of the regulator to be unable to deliver 6V. For there to be 3V at the regulator output, the resistance of the load must be about the same as the equivalent series resistance of the regulator. 

The regulator has a 0.072 ohm 90W resistor that all power must flow through. If that were the ESR, just to make a simplifying assumption, then the resistance out to the short would have to be roughly the same. to create a voltage divider. That resistance is equivalent to more than 50 feet of 12 gauge solid wire, while the size of the 1130 and its use of stranded wire make this very unlikely to be the cause.

The other area of suspicion is that this is a defect in the regulator. That is either caused by out of spec parts values or a defective semiconductor device. 

I have ordered a complete set of replacement resistors to bring all the values in line with the design. I should be replacing them midweek and testing again. If the problem persists, I have seven semiconductor parts that may be at fault. Intermittent contacts in the germanium transistors or oxidation defects on the transistor could be occurring, although why that will happen only in the repower scenario is a mystery. The same is true for a zener diode and a regular diode that are part of the comparator on the card. 

The failure scenario involves the regulator driving insufficient current to produce 6V across the load. That may be a clue to the part of the regulator circuit that is failing in the repower situation. However, it could be due to a number of different parts malfunctioning or being off value. 

The regulator has six germanium power transistors (IBM 108 transistor type) in parallel to deliver the current needed for a 6V output. The six power transistors have their base junctions driven by another 108 germanium power transistor mounted on the regulator's SMS card. If we call this the drive transistor, then its delivered current is controlled by a cascade of two smaller transistors, a type 086 controlling a type 123 that feeds the base of the driver 108 transistor. 

The regulator heart is a pair of type 026 transistors set up as a differential amplifier with a shared emitter resistor. One transistor is driven by the output voltage, using an adjustable resistor to fine tune the target voltage. The other transistor is set with a Zener diode to a fixed reference voltage. As the actual voltage rises above or falls below the target, current through one of the 026 transistors moves to decrease or increase the current into the 086 transistor. That lowers or raises the current through the 123, the driver 108 and then the six power 108 transistors, restoring the output voltage to the target. 

Ordered new components for 6V regulator SMS card for IBM 1130

REPLACING ALL RESISTORS

I found a few with significant drift but most were off nominal enough to warrant my replacing all of them. I ordered the correct parts from Digikey and should have them early next week to swap onto the board. In the interim, I will put the card together with its existing parts and do some other debugging of the issue where the regulator's circuit breaker trips on power-up if the system had been on for a while and only recently powered down. 

Dealing with power supply breaker trips in IBM 1130 6V regulator

BACK AFTER EXTENDED TIME AWAY

My wife planned a big party for my 75th birthday that involved significant planning and setup in advance. Just prior I was down with a long viral infection - not flu nor covid, just a mystery ailment circulating in the area - then a nasty cold struck right afterwards. Add in quite a few other obligations and visits and the result was a long period when I was away from the workshop. Happily I am now back.

SPURIOUS CB TRIPS IN 6V REGULATOR

For some time the 1130 would trip the breaker on the 6V regulator when powering back on after the machine had been off for short periods. I also saw some random shutdowns while operating. I had found a weak circuit breaker and replaced it previously, but the issues did not go completely away.

A power supply in the 1130 takes the input mains voltage and produces unregulated DC (nominally 13V) from a halfwave rectifier that is then routed to the regulator module which outputs a well regulated 6V to power the SLT logic in the machine. The regulator module has a circuit breaker that protects it from shorts on the 6V rail but also has an over-voltage protection circuit. 

If the voltage goes too far above 6V, this will fire a silicon controlled rectifier (SCR) to put a dead short across the output of the regulator, forcing the breaker to trip. The SCR fires in tens of microseconds, limiting energy delivered to SLT circuitry in an overvoltage situation. The circuit breaker can shut off in a more leisurely timeframe since the output is clamped to zero. 

The regulator module has two SMS cards plugged into it, one that does the regulation and the other that provides the overvoltage protection. 

CHECKING FOR EXCESSIVE CURRENT DRAW

I placed a voltage and current meter on the inputs to the regulator - the unregulated DC coming from the power supply - to see whether the draw was close to the limit of the circuit breaker. If it was operating near its trip point, it might be susceptible to tripping on the power up surge. The 6V regulator is designed for up to 24A supply, but when I monitored the operation it never reached 7A, thus I believe the output of the regulator is safely below the rated capacity. 

One issue I observe is that the unregulated DC input voltage is just over 15V, but the filter capacitors in the power supply for this input have a 15V rating. Further, the documentation lists the nominal value to be 12V, with the actual about 32% above that. 

The power supply has a wiring diagram to support 115, 208 or 230V input power. My workshop is set up for 230V and the wiring is set for that voltage. I have noticed that the unregulated 48V and 12V rails are also running hot by about 10%. Those two are fed from a different transformer that was also wired for 230V. 

The higher input voltage means that the power supply would have to drop more power to achieve a 6V output, however the current is still well below the capacity of the regulator. I am mildly concerned that the voltage is above the capacitor rating. There is some safety margin, but I might want to replace the two filter capacitors with ones with a higher rating. 

The only mechanism I can imagine for the over-voltage from the power supply is if the primary windings have some turns shorted together, so that the turns ratio increases to drive up the secondary voltage. It would require about 20% of the windings to be bypassed to produce the observed voltage. 

The home for this system once I am done with the restoration is in a facility with 208V mains, thus if I leave the wiring as it is, the voltages will be lowered. Nothing I can do in my workshop, however, except to replace the transformer which would be wasteful. 

The transformer has two primary windings that are either put in series or parallel to support the 115, 208 or 230V line voltage. For 208, the jumper you can see from 1 to 5 above would instead be connected between 1 and 4 on TB-1. That reduces the number of windings however since we appear to have too few windings as is, I would leave the jumper at 1 to 5. 

TESTING OVERVOLTAGE SMS CARD

I pulled the SMS card and hooked it to a bench power supply with overcurrent protection. The strategy was to run up the voltage past 6V until I observed the card clamp the output to a short. The card has a 150A SCR acting as the final clamp, although I set my bench supply to trip out at a much lower current. 

The card clamped the voltage at 6.5V, which seemed like a reasonable setting to protect the circuitry and is well above the adjustment of the regulator at just over 6. Since this may be triggering a bit aggressively I altered the potentiometer to increase the voltage where it would fire. 

In comparison the card for the 3V regulator clamps at 3.4V. The same percentage over for the 6V supply would be a trip point at around 6.8V. That is what I set. 

The problem continued. Whatever causes the breaker to trip occurs even with this higher set point. Thus we have a few possibilities left to chase down:

1. Component issues or drifted values on the SLT regulator card cause it to produce a voltage spike above 6.8V as it is powered up with only a short period of downtime (a few minutes or less). 
2. Some component in the SLT logic downstream from the regulator will short when power returns after a short period of downtime but does NOT short in steady use and clears itself after a few minutes waiting before the next power up attempt.
3. Some component on the regulator has an intermittent connection that is opened by the heating of the parts, which works properly when powered but surges on a repower after a brief downtime. 
4. Some defect in the unregulated power supply produces a surge on a repower after a brief downtime that somehow overwhelms the regulator briefly.
5. The replacement circuit breaker I bought on eBay has the same defect as the original part in the regulator, where it heats up inside the breaker during use and makes it susceptible to tripping during a repower. 

TESTING COMPONENTS ON REGULATOR BOARD AND REPLACING DRIFTED PARTS

I began pulling resistors and capacitors from the SMS board and testing them. I found a few that had drifted too far from their nominal value, which I replaced with new parts. I don't have a source for new-old-stock germanium IBM transistors, but do have some parts available on spare parts boards. Thus I could put each diode and transistor on my curve tracer and validate its behavior then replace any that are bad. 

Germanium transistors often failed due to corrosion either where the lead enters the can or on the actual germanium surface. Silicon forms a protective oxide but germanium does not, thus leaks in the can lead to failures in the transistor behavior. A corroded lead might yield intermittent connectivity as heat causes the can to grow during operation. 

Testing fully assembled new 1130 MRAM board - read retriggering solved!

TESTING FULLY ASSEMBLED BOARD ON TEST BENCH

I put the finished board on the bench and tested it by triggering a read (rising edge of +Storage Read signal) and watching the sense output lines. I wanted to see multiple 1 bits being emitted for a given read, with the output lines pulled down to ground for 80-100ns for all the bit positions that have a 1 value. There should be one pulse for those bit positions and no retriggering causing subsequent pulses every 800 ns after the first one. 

Everything looked good with this testing, so I moved on to the 1130. I frankly didn't do a lot of detailed testing on the testbench because it was cumbersome to move the probes around. For example, I didn't try writes nor changing the address bits to verify that different locations preserved their contents independently. 

TESTING FULLY ASSEMBLED BOARD ON 1130

The PCB was connected to the 1130 system and everything was powered up. I used the rotary mode control to set the machine to Display mode, where each push of the Prog Start button will drive a storage cycle - a read followed by a write. That will raise the +Storage Read line at first which is what will allow me to watch the sense output pulses. 

Having first set the mode switch to Load mode, I loaded memory with various values then turned to Display mode. I want to watch the output pulses on selected bit positions, seeing only a single pulse not spuriously retriggered pulses. I also wanted the value latched into the Storage Buffer Register (SBR) to match what I had stored. 

Instead I saw somewhat random bits showing up in the SBR and the scope pattern for the sense output pulses didn't make sense. I was seeing two 80-100 ns pulses, one shortly after +Storage Read went high and then another at the proper time. I didn't see that occurring on the testbench.

FOUND BAD CONNECTION ON WRITE TIMER CHIP

I realized that in most cases, the same data patterns came out for various addresses as I did Display operations. I was not able to store any different data patterns into RAM, but it was returning deterministically (to at least a superficial level of testing). I then discovered a pin on the write timer chain (first of two timer chips) that was not soldered reliably to the pad. After correction, I could write patterns into RAM. 

ORIGINAL RETRIGGERING ISSUE FIXED

I was not seeing any spurious retriggering beyond the duration of the read portion (1.8 uS) of a storage access, which means that the original bedeviling problem has been mastered. It was kind of a stab in the dark to add in the separate transistors to drive the sense output pulses instead of using the open collector logic gate that produced the pulse. 

I then had a eureka moment when seeing the pulses occurring very soon after the start of the +Storage Read high signal. I noticed that a second pulse at the correct time was happening whenever the board was returning  a 1 bit in that position, while the first pulse seemed unrelated. 

EUREKA MOMENT

Realization rolled over me at that moment. I realized that my sense output pulse, which is a transistor pulling a line down to ground for 80=100 nanoseconds, wasn't connected only to the flipflop that would turn on for the falling edge. There were multiple gates connected together in what IBM calls a wired-OR. That is all the output wires from the various gates are just shorted together - with each of them acting as an open collector driver - so that any of them could activate the flipflop. It was not only a sense output from core memory that turns on the flipflop.

What I was seeing was other gates hooked to the flipflop creating a setting pulse for some other reason. The various gates that produce pulses to set the Storage Buffer Register bit position to 1 are:

• IO bit is gated to B register (SBR) - peripheral  controller drives this
• I (Instruction Address Register) is gated to B 
• A (Accumulator Register) is gated to B
• Core sense output pulses sets B

I don't know what would produce one of those pulses during the T0 clock phase of the read cycle, where I was seeing the pulse on the 1130 side. The gates above should only operate if the machine is trying to store something in a memory location - the IAR, Accumulator or an IO controller word - which should not be happening here.

My next round of testing will focus on what is causing this T0 gating to the SBR. I don't understand why this would happen during a Display mode storage cycle. Either this is a defect somewhere in the 1130 that needs correction or it is a normal behavior that does not cause problems when IBM core memory is used. 

These pulses are pulling the input of the flipflop called the "AC trigger" down to ground, discharging a capacitor that was charged up by the enabling line to the AC trigger. If the capacitor is discharged fast enough and for long enough, the flipflop changes state. It requires about 8ma of current sinking to achieve the setting of the flipflop, times each bit position that has it flipflop set. That is up to 18 flipflops (for a word of all 1 bits).

It appears that something occurring during the discharge was being injected back into the 1130 MRAM board through the supposedly open drain NAND chips. Probably a negative excursion of the line which pulled down the VCC of my board enough to cause the ringing and spurious retriggering. The replacement of the NAND chips with an AND followed by a discrete transistor seemed to resolve this as the transistor could handle the short reverse voltages without any interaction with my VCC and ground planes. 

SOME MANUAL OPERATIONS TESTING THE BOARD

Using the LOAD and DISPLAY modes of the 1130, I was able to put in contents to specific locations and read them back. This is a mode where you take a single storage cycle, pushing the Prog Start button to display or load at the current address. These seemed to be working properly.

I then used the STORAGE LOAD and STORAGE DISPLAY switches on the CE (Customer Engineer) panel to load patterns to all memory locations in a loop or to loop through reading all memory locations. Storing a value of x0000 worked correctly, always returning zeroes. However, when I set the pattern to something else, such as xFFFF, the load appeared to be working but when displaying I got back variable random data and parity errors. 

Since parity is generated on my board based on what is read back from the RAM chip, the only way to see a parity error on the 1130 is if the data being latched into the SBR is not what was read from the chip. This suggests a timing issue or another problem that may be happening during continuous successive storage cycles such as the looping of STORAGE LOAD. 

During my next round of testing, I will examine what is happening during continuous storage cycles and look for defects either in my design, the current board or the 1130. 

Testing attempt on new 1130MRAM board

PCB AND STENCIL FABBED BY JLCPCB.COM

I used my long time PCB fabrication house, JLCPCB.COM, to build the four layer board. Once again it was easy to upload the design, configure the board to my specs, pay and watch the progress as it was manufactured. I also uploaded the design to create a stencil for the top layer of the PCB.

The stencil came in a larger separate shipping package with wood boards sandwiching the thin aluminum part. My PCBs came in a smaller blue box, shrink wrapped and padded. I selected DHL two day shipment. The parts were made on the promised schedule and the boxes arrived one day earlier than expected. 

TESTING OF PARTIALLY ASSEMBLED BOARD WITH TEST BENCH

I produced a rising edge on +Storage Read and watched the sense output lines for the output pulse. The goal is to see pulses on all eighteen output pins. Further, there should be one and only one output pulse per rising edge of the input trigger. 

The bits were all treated as if they were 0 value, thus no output pulses. I did see the timer chain output pulse. Based on this, I believe have to assemble the board completely in order to test its behavior properly. 

BUILDING THE FULL BOARD

I removed the components from the prior board and installed them on the new board. For each, I used a section of the stencil to lay down solder paste over the solder pads, placed the part atop the board and used my heat rework tool to melt the solder. 

I also had to harvest all the decoupling capacitors from the backside of the old board and install them on the new PCB. One disappeared into the mists as I tried to install it, snapping off the tweezers with which I was holding it, but I had spare capacitors on hand. 

TESTING CONNECTIVITY OF ALL PINS

I used by PCBite test platform to hold the PCB while I placed probes on each pin in turn, putting a probe on a remote pin that should be connected to the same net. It took a while to beep out several hundred pins but the time was well invested as it gave me confidence that I didn't have any bad solder joints. 

Interim method won't work; assembling new PCB

FASTER 2N2369A TRANSISTORS TRIED

The same setup with the square wave generator was used with the faster 2N2369A transistor and I did see a substantial improvement, with the pair of transistors operating to about 4.4MHz although the waveform was very distorted. The first transistor signal was better than the second, where irregularities were multiplied. 

The circuit on the new PCB has a single transistor driven by an AND gate but the interim method has a NAND gate on the old board so I needed to invert its output with a first transistor before driving the second one. The other issue is that I need the special board to intercept the signals on the ribbon cable, wires tacked on and a breadboard to host the transistors. 

Turns out that the capacitance and other consequences of the all the above will cut down on the max frequency I could handle. The new PCB with its short controlled traces will undoubtedly operate faster - hopefully up to the 10-12MHz rate of the memory system. 

BUILDING NEW PCB IN STAGES

I received the new PCBs, the stencil, and the parts while I was on a roadtrip to pick up a 3179 color terminal in Atlanta. I decided to assemble only the components I need to determine if my approach will stop the spurious retriggering issues. Since this occurs when many bits of a word have a 1 value, causing many of the sense output lines to be pulsed at the same time, I prepared the PCB to produce that situation when the 1130 attempts a read. 

I had to install the connector pins, the power regulator, the five AND gates, the 18 fast transistors, the two timer chips and the logic IC, plus resistors and capacitors. These will produce the timer pulse when the +Storage Read signal has a rising edge, causing the transistors to pull the output line down to ground for any bit position where the input appears to be a logic high (1). 

I am hoping that the AND gate will treat the floating input pins as a logic high, thus generating an output pulse when the timer pulse occurs. The previous NAND chips acted that way. If it does. then the partially assembled board will emit a pulse on all eighteen output pins, the maximum stressing condition for retriggering. 

The IBM 1130 can be connected to the PCB by the three ribbon cables. When the 1130 issues a read (+Storage Read goes high) and +Storage Use is high (floating pin is treated as a high), the board will produce 80-100 nanosecond pulses about 800 ns after the rising edge of the read request. 

BIG FAN OF USING A STENCIL

The stencil is a thin bit of aluminum with holes cut into it in the shape of every solder pad. It is held on the PCB and solder paste is forced into the holes with a putty spreader. The stencil is pulled up, the components are placed on the board and hot air is used to melt the solder and bond the pins to the pads. 

I used tin shears to but the stencil, removing each section as I soldered down components. Otherwise the previously installed parts would block the stencil from laying flat on the PCB. This means I can't use it for additional PCBs - a one time use - but I will happily order another once this board is fully tested and worth duplicating.