1130 MRAM testing observations while I wait for the new board for the updated design

PCB AND PARTS ARRIVING ON MONDAY

I had redesigned the board to utilize an FPGA to drive all the timing, dropping the use of timer chips and simple combinatorial logic. The FPGA code was developed, simulated, and I loaded the bitstream into the new Digilent CMOD S7 board that will be installed of my new PCB.  The PCB blank and some final components are due to be delivered on Monday, so that on Tuesday I can build the new board to begin testing. 

OBSERVATIONS DOING MANUAL DISPLAY AND LOAD MODE CYCLES

When I set the rotary mode switch to Load or Display and push the Prog Start button, the 1130 takes one memory cycle and either loads memory with the value set in the Console Entry Switch (CES) toggles switches or reads the contents of the memory location and shows it on the SBR lights. 

I was able to load patterns and get reliable readback until I got over about five 1 bits in a word. At that point, some of the bits did not display correctly when read back. A pattern with four 1 bits would be reliably written and read back - this may be more than four bits because there may be parity bits in addition to the data bits that have a 1 value. 

The new design will set only three bits at a time, skewing the setting across multiple 85 ns cycle times of the FPGA. Thus whatever is causing the issue observed should not recur. 

When words with a high number of 1 bits are loaded, I would observe that when displaying, some words would come back as all zeroes while others either had the pattern or the pattern with some of the 1 bits missing. 

The final anomaly that I observed was that when resetting the 1130 using the Reset button, from time to time the value of the word at location 0 was erased instead of having its previously written value. This may be a fault caused my prior design where it reacts poorly to the instantaneous changes in signals during the reset and as the processor comes out of reset. 

Since my new design changes how the control signals are generated, now using the FPGA onboard, this issue is probably not going to recur. An advantage of having shifted to an FPGA for timing and control signals, is that I can change the behavior with changes to Verilog code and update the FPGA board without requiring hardware changes. 

Looking at 6V regulator SMS card to resolve 1130 power issues - part 3

CIRCUIT OPERATION TO MAINTAIN 6V OUTPUT VOLTAGE

The comparator that controls the voltage of the 6V supply is formed with a pair of 026 transistors sharing an emitter resistor. One is fed a 3V reference voltage from a Zener diode, while the other side is fed a fraction of the current output voltage. 

The reference voltage (3V) acts on the base based on the emitter voltage, which is produced by the voltage drop on the emitter resistor from the summed currents flowing through the two 026 transistors. As the current goes up in the emitter resistor, the current draw of the reference voltage side decreases meaning that the other 026 has its current increased due to the output voltage being above its 6V target. If the output voltage drops below 6V, the current in the reference voltage side has to increase since the emitter resistor current lessens. 

It is the output current of the reference voltage side 026 that drives the power transistors through an amplifier to pass more or less current to the output. Voltage drop in the load is based on the current flowing through it, thus more current increases the voltage on the output terminals and less current causes the output voltage to drop. 

OBSERVED BEHAVIOR DURING FAILURE - WHEN THE CIRCUIT BREAKER WILL TRIP

The output voltage is oscillating (with small voltage swings) around an average of 3V when I see the regulator then trip its circuit breaker. This happens when I power up the system when it has been previously powered and turned off for only a short period. 

This implies that the output current is lower, since the voltage is caused by voltage drop in the load (1130 circuitry fed by this regulator). This is paradoxical however because if the current from the regulator is low, then the draw through the circuit breaker should also be low. Instead, it trips in about one second. Thus, a defect in the regulator that causes it to feed insufficient current to the load should not produce the breaker trip. 

AREAS TO LOOK AT THAT MIGHT CAUSE THE SYMPTOMS

If the load were to demand far too much current (partial short), that would result in the observed symptoms if the regulator were unable to push enough current to meet the demand. The regulator has a capacity of 24A at 6V, based on using six IBM 108 transistors in parallel. We would have to see a demand well above that, perhaps 50A, to sag to 3V and trip the circuit breaker. This would be a failure out in the load, not in the regulator.

However, using my LTspice model, imperfect as it is, I was able to reproduce the failure mode if one of the 026 transistors were to form a short across the emitter and collector. It is the transistor that samples the output voltage. I turned my attention to the 026 transistor. 

STUDYING 026 TRANSISTORS ON THE CURVE TRACER

I grabbed a couple of 026 transistors from a donor board and watched them on the curve tracer to see what a good transistor looks like. I then removed the 026 transistor in question from the regulator and watched it. I also examined the remaining 026 from the regulator since I want some balance between the two transistors if I have to replace one. 

There was no problem at all with the 026 transistors when I tested them. I checked all the transistors on the board and they all worked properly. Same with the Zener diode and the regular diode. Based on this I instrumented the board so that I could observe how various points behave when the card is both working correctly and misbehaving. See my prior post where I was unable to reproduce the failure mode once the instrumented card was reinserted in the regulator. 

Watched pot syndrome - can't get the 1130 6V power regulator to trip now that it is instrumented

REMINDER OF THE 6V REGULATOR ISSUE

The 1130 logic rails are +3V, +6V and -3V in addition to some special voltages for other purposes. DC is produced in a power supply unit and fed to voltage regulators that produce the three logic voltages. The regulator for +6V is where the issues arise. A circuit breaker on the regulator will trip if the current demand is too high; in addition it will trip if the output exceeds a voltage threshold and triggers an overvoltage clamp. 

If the 1130 has been previously powered up but is turned off for a relatively short period, when it is turned on again, the circuit breaker would trip. I monitored the current being demanded through the regulator and found that it did NOT go to high levels when the problem occurs. I verified that the overvoltage clamp card was not firing. 

When I watched the output voltage, I would see 6V during normal operation but when the circuit breaker trips, the output was around 3V and I could see it oscillating a relatively small amount around that average. 

I replaced all the resistors on the regulator control card and tested some of the transistors on my curve tracer to see if I could find a semiconductor that would fail if it was hot from prior operation. I didn't find anything suspicious. 

INSTRUMENTED FOUR SPOTS ON THE REGULATOR CARD

Circles around four wire taps

I soldered wires to four spots on the regulator card, in order to have four traces recorded on my oscilloscope. I wanted to see how the circuit behavior changed when it went to the 3V oscillation before tripping the circuit breaker. 

MANY POWER CYCLES ATTEMPTED WITH NO ISSUES ENCOUNTERED

I hooked up the scope and powered up the 1130. I then tried for an hour to run it for various lengths of time, power down for a short while and bring it up again. It NEVER tripped the CB nor dropped the output voltage to 3V as it had been. Everything I tried failed. 

This is an example of the watched pot that never boils. At this point I have to assume that something I did while tacking on the four wires to the regulator board is the reason that it no longer failing. That might be a cold solder joint or a cracked trace. I will have to examine the board very very closely at the four points where I added the wires. 

New rotate and tilt tapes for the 1053 typewriter of the System Source Museum's 1130

TAPES SNAPPED ON THE CONSOLE PRINTER OF THE SSM 1130

The console printer (1053) of the 1130 computer is based on the IBM Selectric typewriter. It has a rotating and tilting typeball that moves across the print line while the paper stays fixed in position rolled over the platen (roller). The typeball on the moving carrier will spin or tilt to type one of the 88 characters on the ball. 

A pair of metal tapes connect to the moving carrier and are threaded over pulleys on the two sides of the typewriter - when the pulleys pivot they turn or tilt the typeball regardless of where the moving carrier is sitting along the print line. There are reasons why the metal tapes may break, thus requiring replacement. A misadjusted typewriter can stress the tapes, the tape might have had a crease that leads to metal fatigue breaking, or people turning the typeball by hand might put too much tension on the connectors at the ends of the tapes. 

I suspect that visitors to the museum have played with the typeball one time too many and caused the tape to snap during operation, as the broken tape and its partner had signs of such abuse. It is very tempting to touch the typeball, a natural reaction to curiosity for someone seeing the Selectric mechanism operating for the first time. I think it will be important to add a plexiglass box over the typewriter to protect the ball from someone twisting it. 

BOUGHT NEW TAPES AND INSTALLED THE ROTATE TAPE FIRST

The museum dropped off the 1053 during a recent trip to Florida and I removed the old tapes. I ordered new ones, as fortunately there are still plenty of spare parts available on places like eBay. Today I installed the tape that spins the ball. 

The typeball is mounted on a coil spring to provide rotary tension. One end of the tape is connected to the disc that holds the coil spring. First the type ball is turned to wind up the coil spring, then the typewriter is triggered and manually cycled to the halfway point of a typing stroke, where a lever locks the ball from turning; this keeps the tension on the ball while the tape is installed.

One end of the tape has a T shaped hook that fits into a slot on the coil spring holder disk. It is threaded out of the movable carrier and routed to the left where a pulley is mounted on a lever. A selection mechanism in the typewriter will pivot the lever and pulley to one of eleven positions, which are intended to rotate the typeball left or right up to five steps of about 16 degrees.  

Slot for T shaped connector

The tape goes round the pulley and then is routed from left to right side of the typewriter passing underneath the carrier. As the pulley pivots out or in, it pulls on or releases the tape to cause the typeball to turn.

Left pulley on lever

On the right side of the typewriter frame is a lever with a pulley on the end. The lever pivots to move right or left, which would pull on or release the tape as it pivoted. This pulley pivots between two positions, intended to place the typeball in the middle of one or the other hemisphere, so that it can access one of 44 characters on that hemisphere; traditionally the hemispheres were for upper case and lower case characters. The tape goes around this pulley and then routed back to the left. This end of the tape has an eyelet attached which will hook over a screw on the right side of the carrier. 

Right pulley and shift lever

Once the tape is correctly routed and attached to both the disc and the carrier screw, the typewriter manual cycle can be finished to release the lever so the coil spring can wind up the tape as the ball turns. With the tape in place, the lever on the left frame selects a rotational position for the ball and the right side lever pulls enough to spin the ball 180 degrees to pick which hemisphere to use. 

Tape path

NEXT STEPS - TILT TAPE AND ADJUSTMENTS

Another tape with pulleys is used to tilt the typeball so that it selects one of four rows around the ball. A typeball has eleven rotary positions and four rows on a hemisphere, thus containing 44 characters on each side and 88 for the full typeball. I have to attach the tilt tape on my next visit to the workshop.

The metal tapes can stretch very slightly over their lifetime, plus manufacturing variances mean that the position of the typeball with replaced tapes may not be at the exact same position as it was with the prior tapes just before replacement. As a result, a sequence of adjustments must be made to ensure that the typewriter will tilt and rotate the ball so that the character to be typed is centered vertically and horizontally as the ball strikes the ribbon and paper. This will be done after the other tape is installed.

Code written and simulated for FPGA in new 1130 MRAM core memory replacement design

ROLE OF THE FPGA

The FPGA produces all the control signals that drive the other chips on the PCB. I can update the FPGA and modify the control signal behaviors without having to create new versions of the PCB. 

The Magnetic Random Access Memory (MRAM) chip has three control signals that are used to cause it to read the contents of the currently addressed word and put the bits on the data bus or to write the values on the data bus into the currently addressed word. These are the E, W and G pins which are active low and must conform to timing specifications and sequences defined for the MRAM chip. 

The MRAM data bus is bidirectional, either outputting the value read from memory or accepting new data to write into a memory location. The control pin G sets the data bus to output the data values. Data that we want to write into the MRAM chip, coming into the PCB from the 1130 Storage Buffer Register (SBR), has to be driven onto the data bus, but not when the MRAM is generating the bits while signal G is active. A Gate control signal is used to control a buffer chip, so that it is either high impedance or driving the SBR bit values into the MRAM data bus. 

During a read cycle, after the MRAM has put the memory word on the data bus, output chips can pull the 1130 Sense lines low to set an internal 1130 register bit to 1. They will only do this if the bit value on the MRAM data bus is a 1, and only when a control signal allows the output to occur. Testing prior versions of the PCB has exposed issues where the output bits work well if the total number of 1 bits in a word is small, but above a certain number of 1 bit values, the word is not correctly stored in the 1130. 

To help with this, the FPGA has individual control signals for all 16 data bits and the two parity bits for the word to be output. My first version of the FPGA logic will turn on control signals for three bits at a time, skewing the transfer of the word value into the 1130 across six clock cycles of the FPGA - each cycle being approximately 83 nanoseconds long. I could changes this to nine cycles of two bits each, or some other combination. However since a read cycle is only 1.6 microseconds long, trying to put each of the 18 bit values in its own clock cycle would take almost the entire read cycle. 

Since the 1130 control signals such as +Storage Read are asynchronous to the FPGA clock, I have to use a chain of flipflops to synchronize and protect against metastable issues. That adds up to four clock cycles before the logic recognizes a read and begin emitting control signals. We also need a cycle or two to make the MRAM read before it places the data values on the data bus of the chip. Adding all those up, a read with all 18 bits on their own clock cycle would take 2 microseconds, exceeding the window of time available for the 1130. 

VERILOG WRITTEN AND SIMULATED

I created the logic for the FPGA using the Verilog language. It monitors the hardware reset signal I generate from the PCB, then watches the 1130 for the control signals +Storage Use, +Storage Read and +Storage Write. Based on those signals, it produces the control signals for the rest of the PCB. 

I wrote a testbench and simulated the logic for the FPGA. I verified that it produced reasonable sequences of the control sequences, with correct durations, which should correctly read and write to the  MRAM chip on the PCB. I also saw that the pulses into the 1130 when a word is read are skewed in groups of three bits, to limit the total current flowing across the cables at any instant. 

BITSTREAM GENERATED TO LOAD IN DIGILENT CMOD S7 FPGA BOARD

I synthesized the logic and created a bitstream. This will be downloaded into the Digilent CMOD S7 board, placed in an onboard memory, and used to configure the FPGA on powerup. I expect the FPGA board to arrive during the week and will set up that board with the bitstream. 

WAITING ON THE NEW PCB THAT EMPLOYS THE FPGA

JCLPCB.com is busy building my four layer printed circuit board for the revision of my 1130 MRAM which is a PCB that plugs into an IBM 1130 in place of an entire core memory compartment. I hope to receive the new board as well as some addition components from Digikey by the end of the week or early in the following week. 

The CMOD S7 board fits in the lower left of the PCB in the image above. The MRAM chip is right in the middle of the PCB and the three cable connectors are across the top of the board. 

Testing 1130 MRAM board - defect in design identified

LOCATION ZERO IS SET TO VALUE OF ZERO DURING A SYSTEM RESET

I saw two categories of problems while testing the memory board, now that I have the system power more reliable (but not still fully fixed). First, when more than a few bits are set to 1 values, the data does not seem to be reliably read back into the Storage Buffer Register (SBR). Second, many times when I hold down the Reset button (or at power on reset), the contents of location zero is set to all zero bits. 

I dug into the timing of various signals when the machine comes out of reset and to find vulnerabilities that will result in a spurious write being commanded of the MRAM chip. The logic for controlling the lines +Storage Use, +Storage Select, +Storage Write and +Storage Read produce unexpected values as a reset condition is release, which triggers my board to perform a write operation. 

+Storage Use will be on at any time except for a storage cycle when the 1130 does not want to access memory, thus it is on immediately as reset is released. +Storage Write is on immediately after reset is released and also during the entire time that reset is active. 

It is even possible that this flaw in the design could cause problems at other times while the system is running, but in any case it must be corrected. 

REFINING THE USE OF CONTROL SIGNALS BY MY BOARD

In systems using the faster 2.2 microsecond core memory type, the signal +Storage Select will emit a short pulse when the processor steps into states T0, X0, T4 or X4, which will trigger a storage cycle as long as +Storage Use is also high. In normal processor execution, each storage cycle takes eight T clock steps, T0 through T7. The first half of the storage cycle, T0 to T3, is when +Storage Read is high. The last half is when +Storage Write is high. Thus the IBM core memory logic is triggered by the pulse as long as +Storage Use is high, but does a read or a write based on whether +Storage Read or +Storage Write is high. 

In the 3.6 microsecond memory type, such as the machine into which my board will be installed, +Storage Select is driven by the high address bits to select which core memory compartment is active. In the machine I am restoring, there is only one gate so this is effectively always on. In fact, the core memory logic in that compartment does not even look at a +Storage Select signal since memory in gate B compartment C1 is ONLY used with 4K or 8K configurations of 3.6 uS core. 

MAJOR PIVOT IN DESIGN OF THE BOARD

I decided to ditch the timer modules and instead depend on a small FPGA to handle the timing. I designed around the Digilent CMOD S7, a Spartan 7 board. It has enough input-output pins to make the operation of the board fully flexible. I did have to add a 5V power supply regulator to feed the CMOD. 

Now, the pulse to write a 1 into the Storage Buffer Register (SBR) for each of the 16 data and 2 parity bits is an individual line for each bit. Since the existing board works okay for a small number of 1 bits but fails with larger groups like 6 or more, having individual control would allow me to stagger the pulses across the bits so that any funny analog issues that arise from the simultaneous activation are avoided. 

I also control the individual control signals for the MRAM chip - Write, Data Out and Enable - so that I can refine the timing of the activation if needed. Even the buffer chips which block the incoming SBR bits from the memory during reads but pass them through on writes is controlled by the FPGA. 

This definitely requires a change and a new PCB to be fabricated. I also have to write the Verilog for the FPGA, but that is dead simple for this case. While the board is being manufactured, I can write and test the code. Then, when testing, I can adjust timing of signals to refine the behavior of the board.

Slowly improving ability to use LTspice to model circuits with germanium components

WHY MODEL AND HOW

LTspice is a free version of the SPICE circuit modeling software. Entering a schematic allows the operation to be simulated and graphs to be produced of the voltage and current at selected nodes. Very valuable to understand the operation of a circuit in detail. I also find it useful to modify components to see how they would behave if they are defective, in order to confirm a hypothesis about which part has failed. 

The libraries provided by Analog Devices when you download LTspice include many component, but not every possible part. Usually the Spice model for a component can be found online and added to your schematic. However, there are almost no models online for Germanium transistors and diodes.

IBM USED GERMANIUM SEMICONDUCTORS IN THE SMS AND SLT PRODUCT FAMILIES

Standard Modular System (SMS) was the basis for IBM's transistorized computers in the 1950s and early 1960s. Solid Logic Technology (SLT) as the basis for the 1960s and 1970s computers such as S/360 and 1130. The diodes and transistors used in both families were Germanium based. 

While the industry was transitioning to Silicon semiconductors which are much better for most purposes, IBM needed massive quantities of transistors and diodes, including manufacturing their own. Staying with Germanium assured them of adequate supply and avoided the need to re-engineer many circuits. Similarly the industry was beginning to use integrated circuits (ICs) in the 1960s but IBM's volume needs and other factors led them to stay with discrete transistors and diodes in the SLT generation. 

IBM used many different transistor types in their products in SMS. In SLT, the transistors and diodes used in the SLT modules were much more standardized but SLT cards often included separate transistors in a myriad of types. 

SPICE MODELS FOR GERMANIUM SEMICONDUCTOR COMPONENTS

There are only a handful of models to be found on the Internet for Germanium transistors. Music effect pedals make use of Germanium because of the way that signals are distorted by the device's characterists - pedals such as a Fuzz box - which is by far the largest use of Germanium today. Thus, the few transistors that are used in effect pedals do have some models to be found. 

However, there were many hundreds of different Germanium transistors sold, the vast majority of which have no models online. IBM made use of almost 200 transistor types for SMS and SLT. This is where my problem lies.

GERMANIUM VERSUS SILICON GROSS BEHAVIOR DIFFERENCES

Silicon semiconductors tend to have a turn-on voltage across the base-emitter junction of around 0.6V while Germanium semiconductors turn on at much lower levels. typically 0.1 to 0.3V. The operation of a transistor with a given voltage at the base can be very different between Germanium and Silicon, as a consequence. 

Germanium transistors operated in reverse mode (switching the emitter and collector) work better than Silicon transistors in the same mode. The amplification factor (beta) is less in reverse mode, but at a reasonable level with Germanium. Other characteristics worse for both types in reverse mode, but there are some circuits (especially effects pedals) that chose to use the transistor in reverse mode. 

Germanium devices have higher leakage currents and are less stable under temperature variations than Silicon. They also are more susceptible to failure due to air leaking into the package than Silicon. Silicon forms an insulating oxide when exposed to air, which limits the impact on the device, while Germanium does not. Finally, the way that the component leads enter the typical Germanium package were susceptible to breaking or corrosion forming at the entry point. 

IBM labeled their transistors and diodes with their own designator, even if the part was procured from an industry source who sold the same part with an industry recognized number. Thus even if a model had existed for a particular transistor under its commonly known number, to model an IBM circuit required knowledge of the IBM to industry standard number translation. 

GRADUALLY EXPERIMENTING WITH SPICE MODELS FOR SOME IBM CIRCUITS

I have been hacking at some models that exist for Germanium devices, trying to get the IBM circuit to operate as it should. I have found a table that circulated among IBM repair people (Field Engineers - FEs) during the SMS era that purports to list industry standard transistors that could be substituted for an IBM numbered transistor in a pinch. These may list five or six different transistors, thus making clear that the substitute is NOT an exact match. 

I have located some spec sheets for the industry standard transistors in that substitution table and from that I have worked up a potential set of specifications for the IBM part, such as hFE and Vceo, that would be the basis for a spice model of that IBM part. This is challenging because a spice model does not have entries like hFE, but instead has a myriad of parameters as you can see below:

My challenge is to turn the potential specifications I derived such as hFE into the parameters above. This is a work in progress. It will be quite valuable in the long run to be able to model IBM circuits accurately.