Finding and fixing errors, routing manually since KiCAD has no autorouter function

CONNECTOR NUMBERING WRONG FOR FPGA

The Ztex FPGA board has twin 32x2 connectors, standard 2.54mm spacing, with one labeled D and C for the outer and inner rows, with pins numbered 1 from the bottom to 32 at the top. Thus there is a D9 and a C9 on that connector, but the pin numbering schemes in the library are all numeric. 

I thought I had selected a reasonable scheme that would number pins 1 to 32 for the C side and 33 to 64 for the other, but when I began the routing I found that the PCB layout didn't match the schematic layout. Instead, it assigned 1 and 2 to the D and C sides at the bottom, the next row up was 3 and 4, and it continued up to 63 and 64 at the top. 

This manifested itself in strange paths where I had laboriously laid out the components to minimize crossing and distances between the connector pins and the components. Also, 3.3V power and ground were mostly assigned as rows, so that the C and D pin of the same number were assigned to the same power function. As it sat, however, none were in common rows.

I made a copy of the layout entry for the connector and carefully edited that copy to have the pin numbers as I wished - the bottom right side started at 1, ran vertically up the right side to 32, then started over with 33 at the bottom left and finished with 64 at the top left. This produced much more reasonable positioning for the traces I would be routing. 

SWAPPED AND SHORTED SIGNALS

In a few spots I found that the schematic editor had created junctions where I hadn't intended them, thus shorting two signals together. Another path was open, I failed to connect the trace all the way in the schematic 

Those situations were easy to fix. I found a spot when I was routing signals that didn't make sense. The high speed SPI link header was assigned to four adjacent pins (two adjacent rows with two pins each) but one of the connections went to a very different spot.

I had to resort to a generated netlist and some searching to discover that I had the SPI header pin and the screw terminal for another signal mixed up, each routed to the other's assigned FPGA connector pin. Again, easy to fix once you find the problem. 

LOOKED IN VAIN FOR AUTOROUTE

I am used to having an autorouter as that was included in the past toolsets I used. These are usually not very good, but sufficient to do a first approximation. I would often fix up the oddball routing, tweaking the runs and get a reasonable board out of the process. 

When I looked over the choices in all the menus and toolbars, however, I didn't see anything that suggested autorouting. Some Google searches confirmed that indeed, KiCAD does not include an autorouter. It had something in old versions but that was removed and dropped from the project aims. It is possible that I could find some plug-in from other sources and attempt it, but I decided to continue on doing manual routing for all the remaining signal runs.

HAND ROUTING USING MY SCHEME FOR THE FOUR PLANES

I chose to use the four planes - front, back and two inner coppers - with specific wiring types restricted to each. One of the inner copper layers was the ground plane across the entire PCB other than for holes around vias and pins that don't connect to ground. The other inner layer was used solely to route the 5V and 3V power rails. 

That left the front and back for all the signal paths. It is easier to follow without having interior runs for signals. The bottom layer has only the seven decoupling capacitors for the buffer chips soldered on it, otherwise it is nothing but traces. 

As far as possible I tried to run traces in the order that would lessen crossings and result in fewer vias. I chose locations to cross signals so that, again, the number of vias was lower. I currently have roughly one dozen signals left to route, with everything else seemingly done properly. 

When I return to this tomorrow I will wrap up the final traces and then begin the cleanup and validation phase. I will improve some trace runs for esthetic reasons, then run through and check each net for its proper connection and integrity. The final checks will be physical, ensuring component clearances to the manufacturers drawings are preserved.

Routing nearly complete