BACKGROUND FOR UNDERSTANDING THE SENSE DSW ISSUE
The 1130 has a common input bus for I/O data as well as the device status words, with all the sources for a bit tied together so that any one of them can pull the line to ground to indicate a 1 value. This means that many circuits can be turning on those bits.
When reading from a peripheral, the IO bus is gated into the B bus (memory data register or storage buffer register) at the correct time so that it is written back to the current memory word. DSW status bits are also gated to the B register in the same way.
This means that the issue could also be occurring in the B register, but the IO bus value was correct. That is another avenue to chase down. In addition, there are other registers involved, which I will discuss below.
The 1130 is a memory centric machine, with instruction execution involving one or more memory access cycles. An address is placed in the M register (Storage Address Register) before the cycle begins and the contents of memory are placed into the B register (Storage Data Register) in the midst of the cycle. If a new value is to be written into that memory location, the B register is changed before the second half of the storage cycle takes place.
The instructions themselves are in memory, thus before they can execute they must be read with a storage access. Each memory/storage access cycle is one of a number of defined types. I1 is what fetches the first word of an instruction, but we could need an additional storage cycle I2 if it is a doubleword instruction.
The address of the target of the instruction must be determined and these might require storage access cycles themselves - IA for indirect addresses and IX if an index register is involved since those reside in memory at fixed addresses.
Once all the preparation steps, at a minimum I1 but as much as four cycles I1, I2, IX and IA, then the purpose of the instruction can be satisfied by execution memory cycles. E1 is the first execution memory cycle, where a value might be fetched from memory or placed in memory. Some instructions may not access the memory, instead changing arithmetic or logical data, but that occurs using a storage cycle but setting a signal that suppresses access to the core memory during the cycle.
We see the I register (Instruction Address Register) is moved into the M register before a cycle to cause the instruction's first word to be read into the B register. In the diagram above, a simple instruction has only the I1 cycle and then the E1 cycle to grab the value in the target memory location and place it in the B register.
In the 1130, every memory access produces a value in the B register. When executing the XIO Write instruction, the last memory location we read is the address where the character we want to print is stored, thus B contains that value. When it then starts to execute the XIO Sense DSW (step I1), the first memory address read is the instruction word, which replaces the B register. The XIO step E1 then fetches the second word of the Input Output Control Command (IOCC) which has the device, IO function and sometimes control bits. Thus word 2 of the IOCC is in the B register.
In step E2, the XIO fetches the first word of the IOCC which often is an address but for XIO Sense DSW the storage read is blocked and we instead just gate the IO bus to B register. The XIO Write, step E3, on the other hand, will fetch memory at the address we just picked up. For an XIO Sense Device, the value in the B register is then gated to the D (Arithmetic Factor Register AFR) and passed through to the A (Accumulator) register using a couple of arithmetic logical unit control signals.
Somehow the value in the B register looks more like an XIO Write than an XIO Sense Device. However, the first word of the IOCC I used was not the address where the character value was stored, so it could NOT be actually reading it from memory like an XIO Write E3.
The data that was in the B register multiple memory fetches ago is now showing up in the A register during the XIO Sense DSW step E2. While it looks as if the IO bus for the sense DSW stored the 'saved' value in B, it had no path to make that transfer happen. I think instead this has to do with the D and A registers. They would not be disturbed by the I1 and E1 stages of the XIO Sense DSW instruction execution, thus anything in them would remain there.
The problem with this hypothesis is that the XIO Write should NOT be transferring the B register value to D or A. In order for the observed actions to take place, the XIO Write would have to transfer the B reg value somewhere else, which it shouldn't, then the XIO Sense Device would have to move something other than the IO bus value to B, D and A.
Compare the XIO Write instruction, which is diagrammed above, with the XIO Sense DSW instruction diagrammed below.
The E1 step of XIO Write will grab the second word of the IOCC and store it in the U register to determine which device and XIO function is being performed. The next storage cycle, E2, will grab the first word of the IOCC which contains the address in memory where the character data for typing is stored. That address moves to the M register and the E3 storage cycle causes the character value to be fetched into the B register. The typewriter controller logic looks at the value in the B register to determine how to control the typewriter.
The E1 step of XIO Sense DSW also grabs word two of the IOCC, and another storage cycle takes place as E2. However, the storage access is blocked, nothing goes in or out of core memory. Instead, the typewriter controller logic sets bits to 1 in the IO bus and it is gated to move into the B register. Other signals than gate the movement of the B register to the D register (Arithmetic Factor Register) and control signals cause the value in D to move into the A register (Accumulator). All those gated moves happen during a storage cycle but no actual memory access occurs during that time.
The address in the first word of the IOCC for XIO Sense DSW may be moved to the M register but it is ignored since we have inhibited memory access. The typewriter controller logic is only able to set some status bits in the IO bus. It is not able to write back the entire character value. This is the root of the problem - A register ends up with a value that is long since gone from the B register when XIO Sense DSW starts executing and the controller logic has no way to write it back even if it had it.