Thursday, October 2, 2014

Working on receiver and driver circuits to interface to 1131 SAC


The driver is quite easy, as it is a transistor that will pull the transmission line down to ground or let it float up to the +3V supplied through the far end's 95 ohm pull up resistor/terminator. Doesn't require simulation and testing.


The transmission line is twisted pairs with 93 ohm characteristic impedance, allowed to have up to 33 ohms resistance, with a 95 ohm terminator resistor pulling the receiver end up to +3V. The driver is a transistor that will pull the line down to ground or let if float up.

The challenge is dealing with the maximum resistance case - 33 ohms - as that produces an off state at over .75 volt, well above the SLT specification of .3V max for a logic level 0. The logic 1 case, +3V is well above the minimum of 1.8V and quite satisfactory, even with a bit of loading from a receiver circuit it will meet specs.


I have to design a receiver that will properly yield a logic 0 when the line is above .75V, and generate a logic 1 when the voltage is up close to 3V. If I simply hooked up a standard logic gate to the transmission line, the gate must interpret the .75-.8 volt level as a fully legal binary 0.

I am working on discrete components as a receiver circuit, allowing me to control the behavior and simulate it as I tweak the design. Unless I figure out a standard gate that is sure to interpret my levels properly, the custom design is necessary.

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