SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130
A fellow enthusiast taught me how to filter the messages from the Xilinx toolchain, since I get over 700 'warning' messages from my logic, with very few that really matter. Finding them among the many false alarms has been a headache, but Marc showed me how to filter individual messages.
It was painstaking work as I couldn't select groups of messages, having to select then mark each individual message. However, by the end of the day I had filtered out more than 500 messages that are completely unneeded. I left some messages that reflect intentional choices but will be problems once I fill in some portions of the logic. I can scan through 200 messages to look for real problems I need to address.
I also worked on the restructuring of both fpga and PC logic to make use of the 12 word transaction size. At the same time, I decided on a change to my 1403 printer functionality, putting the virtual carriage control tape and all the logic to respond to it down inside the fpga.
I will begin with a fixed carriage tape, having holes in channels 1 to 8, 10 and 11 on the first 'line' and a hole in channels 9 and 12 on line 66. The PC will still need to know about skips, but I can return that easily so that the PC output file can mirror what a real printer would do. The fpga will model the time that a 1403 takes to accomplish the skips and line spacing. All the PC has to do is cycle steal to fetch the 66 words or less that contain one print line. - two columns per word.