Working on core load function - fpga logic debugging

SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130

Cleaned up the code and kept testing. I was fairly sure that the Python side was packing up the right transactions and sending them in, but the FPGA was not storing them in core nor fetching the contents back. A flaw in my FSMs I have to hunt down.

Study of the code showed one weakness. My FSM that loops through 1 to 11 words of cycle stealing for a CS read or CS write transaction began as we were reading in word 2 of the incoming words, but it should wait until the full incoming payload is latched so that we store the correct data into core. I found a few other more minor issues as well, but stuck in some diagnostics to prove that I was seeing certain signals and states of FSMs.

Two steps forward but one step back. Somehow I am out of sync again on my output words. This will take a bit of headscratching to figure out.