I finally diagnosed the problem and corrected it. I was using an opencores module for the use of the EZ USB link that comes on the Ztex board. The documentation is rudimentary, just comments on the instantiation template.
There was a comment "when DI_READY is 0, DI and DI_VALID are hold". Are hold? That means only switch the value to be written out when the ack signal DI_READY tells me the prior word is accepted to go up to the PC. I though I changed it when I had de-asserted the DI_VALID output. A change to my FSM from a Moore to a Mealy type got me what I wanted.
I moved on to testing the core memory load from the PC file, which exercises my new Python code to pack transactions with up to 12 words, but flush them when a change of core address or other event requires me to write out the previous partial block. I discovered some minor issues but a slightly bigger design mistake I made in the Python code
When reading from core, I could accept a full 12 words by putting the first core value in word 1 of the response, while on most transactions the first word of the response echoes the command sent. However, for writing to core, the first word of the transaction MUST be the command, thus I only can send 11 words in the remainder of the transaction. Oops, clearly didn't think this through.
I modified all the code to handle 11 word transaction packages. Back to testing after dinner. Debugging the packing and flushing code, which ensures that I get the transactions down to the FPGA. I will then have to debug the logic that actually writes these transactions out to the 1130 core memory. Each step requires creation of some debugging instrumentation, thus it moves slowly.