The 1/4 millimeter diameter grit won't arrive until tonight, thus nothing was one on the reader today.
INVESTIGATING MEMORY UPGRADE USING EMM CORE STACK
I began digging through the ALDs and the inventory of what is installed on my machine to see how feasible it would be to make use of this 32K word by 18 bit card to bring my 1130 up to full memory configuration - 32768 words - from its current 16384 size.
|MB301 Final assembly of memory address bits 1 and 2 (16K and 32K)|
For example, on this page there is a note about a jumper which is installed if the machine has expanded storage. It allows bit 2 of an address from the built in disk drive to be gated to memory when the drive is using cycle steal to fetch and store words. Oddly, no jumper is required for bit 1, which is always driven by the disk adapter logic sourced from logic page XF231 same as bit 2.
Sources to the page MB301 that must be checked include the I and A registers, file (disk drive), and the SAC. This page is the M register for the high two bits (1 and 2). This feeds the MB311 page which assembled the final storage addresses going to core storage.
The page does have signals for Card Reader bits 1 and 2, but no card as a source. These represent the signals that would be used if a 2501 were configured, since the IBM 2501 uses cycle steal to fetch and store words.
So, you might ask, why no signals from the 1132 printer, 1442 card reader/punch, 1053 console printer, keyboard or console entry switches? Because none of these use cycle stealing. All the data they need to fetch or store is handled by the XIO instructions themselves, which make use of the A register feed during their execution.
|MB311 which has drivers for the memory address lines bit 1 and 2|
|MB101 assembles CPU address bits 3 to 15|
|MB111 - assembles sources for memory address bits 3 to 15|
Notice that some of the bits have inputs from the printer and the special index register address circuits. When the CPU wants to address an index register, it blocks the M register (CPU addresses) using inhibit and then feeds in a 1 on bit 14, 15 or both depending on whether register 1 2 or 3 is needed. The 1132 printer does a fetch of locations 0x00020 to 0x027 for the bits to control firing the 120 hammers, so it needs to inject 1 bits into address bit locations 10, 12, 13, 14 and 15.
|MB201 allowsprinter and file (disk) addresses only during cycle steal|
The sharp eyed reader will see that the storage address bits 1 and 2, generated in MB301, do not get signals from the M register, don't have a CPU address generated as is done for the lower bits in MB101, but instead create a shadow version of the M reg bits 1 and 2. Looking at the M reg itself on RB111 and RB121, the M reg flipflop is not connected to memory addressing at all, while bits from RB131 (bit 3) and lower use the M reg to build CPU address.
The effective value, the 'shadow' of what is in M reg bit 1 and 2, is held in the flipflops in MB301 and generated independently. It looks at the value of the I and A register for those bit positions, control signals which are active when the M register is loaded from I or A in the RBxxx logic pages, and a special generated signal to load SAR bits 1 and 2. This is logic that is parallel to and different from how the other bits are handled. Odd, since the M register does have bits 1 and 2 present, but the output is only used to display the lamps on the main panel.
|Terminators for storage address signals for bits 3 to 15|
|Cabling between gates of 1131|
For a machine with only 4K or 8K of memory, thus without the expanded storage feature, all memory is placed on CPU gate B in compartment C1. No blister is installed, resulting in the short version of the 1130 system.
Three cables are run - with the pair that hook to the T1 and T4 positions in a wired-or configuration so that any of the core modules can introduce data to the common bus. The other cable runs through each module, coming from the CPU to T2 of the first module, out of T3 on that first module and into T2 of the second module, and so forth. The final module's T3 will have terminators wired up.
My machine has gate D with both compartments filled - yielding a 16K total memory configuration. It is missing gate E. If a machine had 24 or 32 K of memory, it would have gate E installed also and use one or two compartments depending on storage size. I will put my interface logic, power supply and the 32K storage card in the empty area in the blister where gate E would have been installed.
|AD001 lists various jumper wire, cabling and terminator requirements|
If I increase memory from 16K to 32K, I need to add some jumpers on the existing core modules on gate D. These jumpers will deliver 'not bit 1' to the modules, so they are inactivated if bit 1 of a memory address is 1 but active otherwise. My new circuitry would only work when bit 1 was on, so that the new card handles addresses from 16384 to 32767 while the gate D compartments handle 0 to 16383.
The jumper is not on the machine as it sits, because it will allow memory addresses above 16383 to roll over and use the existing memory. What I mean by that is that all addresses are treated modulo 16384. Thus, 0 and 16384 are the same core location. 1 and 16385 are a common location. This is now the 1130 architecture is arranged.
The jumper is added to block that behavior. With the 'not bit 1' added into the selection logic, when an address increases past 16383 it is no longer modulo 16384. It becomes modulo 32768 when I add the new memory card and make use of address bit 1. Address bit 0 does not exist, so address 32768 becomes the same as 0, etc.
This leads to the interesting possibility that a machine could be increased to 64K but with quite a bit of work. Circuitry equivalent to the MB301 card would be needed to produce address bit 0. The SAC logic and disk (file) adapter logic would need to be changed in a few places to include the extra address bit. The existing SAC cable does not carry bit 0, it would need an additional signal line.
The flat cables to the memory do not carry bit 0, so signal lines would have to be added to carry the wider address. Finally, the select logic for the memory compartments would have to take into account bit 0 as well as 1 and 2. There may be other subtle factors, but a few cards worth of logic and some additional cabling would do the trick.
|AD000 Jumper and timing settings for configuration changes|
Based on this, I need no change to jumpers when increasing memory to 32K, but would have to swap the two sets of jumpers if changing to act like 2.2us memory. In that case, the oscillator card has to be adjusted to 3.64MHz (might need a different crystal) from the 2.25Mhz rate it has now. I would have to disable all of the existing core, since it is too slow, and use the entire 32K word new card as memory to operate as a 2.2us model.
The bottom line of all this investigation is that adding in my additional 16K of core should be quite easy, requiring only a few jumpers on the existing memory to look at 'not bit 1', adding cabling to my new interface logic and moving the terminators there. The 0.95us memory of the new card will readily work fast enough.
One complication inside my circuitry when using a much faster memory is that the data to modify a word for the write part of the cycle is not produced by the 1130 until halfway through the 3.6 or 2.2 us cycle, so I have to control how the new card does its rewrite half so it is delayed from 450ns to the 1.1 or 1.8 us point.
Fortunately for me, the EMM card has a mode - split mode - where it does the read half of an operation based on a read trigger pulse (RP) and waits for the user to initiate a write trigger pulse (WP) to trigger the rewrite. Thus, I can control the timing so that I send RP, it does a read in 450ns, waits until I trigger WP at 1100 or 1800 ns, then completes the rewrite by 1550 or 2250 ns.
The data out signals are wire-or connected to the B (storage data) register and will set bits on as soon as nonzero data from the core arrives. Normally this is from the sense amps as the IBM core is read, but I have to be sure that the data is blocked until it is safe for it to appear and that it goes away when necessary. This may work with no such blocking, but it is a need that I have to anticipate.
The rewrite which is done from the B register contents in the 1130 does not care if the data is not ready exactly at the halfway point of a memory cycle, as long as it is present and stable at the time the 2.2 or 3.6us memory is ready to flip cores on or off. The new card will complete the write much faster, so I may need to delay the WP pulse until the point when I am sure the 1130 has the B register value present and stable. This delay is pretty likely to be required.
As far as signal and power requirements, the new card uses TTL signaling levels, although inverted sense so +5V represents a zero logic state, and the memory needs +5, +15 and -15V supplies. The +15 and +5 rails can draw up to 3.8A, while the -15 needs no more than 1.2A. The board needs less than 100W of power and there are many low cost supplies I can buy to provide the power.
I need to provide for SLT to TTL level shifting - with the SLT operating with 0 to 3V signal levels while TTL is 0 to 5. I have already addressed this with my SAC Interface box and simply need to modify that design a bit to snoop on the 15 address bits and 16 'data out' bits coming from the CPU to memory. Then, I need open collector ICs to activate the 'data in' bits when my core is emitting sense bits in to the 1130 for a read. I have to snoop a few storage timing and inhibit lines as well, but that is the same problem as with the 31 data & address bits.
What also must be designed is inhibit logic if I need to control when my 'sense amp outputs' are presented to the CPU bus and to control when I fire the RP and WP pulses into the new memory card. This is the new portion of this design, all the rest being variations on previously solved and proven approaches.