Debugging issue with XIO Sense DSW - part 2

GATING ONE REGISTER TO ANOTHER IS A BIT COMPLICATED

The terminology suggests that you will get an exact copy of the source register in the destination register, but the reality of the circuitry is important to understand. Gating into a register involves IBM's edge sensitive gates, which produce a pulse to set a flipflop for the bit. This pulse sets the flipflop. It does not reset it. The contents of the source will not be turning off the flipflop of the destination. 

Further, the control signal that arms the edge sensitive gate is the bit value of the source. If the source holds a 0 value, then the edge sensitive gate is NOT armed and cannot set the flipflip. It is when the source holds a 1 value that the gate is armed and turns on the flipflop at the appropriate time. We transfer 1 values but not 0 values. 

This may sound like a quibble, but it means the entirely different circuits are involved in resetting the bits of the destination. This would be a register clear signal that turns all the flipflops to 0. Now imagine that the register previously held a value of x3C00 and it was not cleared. If the source holds 0x0800 when the gating occurs, the destination register remains at x3C00. If the source holds x00F0 then the destination register would become x3CF0. We are doing an OR into the destination, so that we absolutely must have it cleared to x0000 before we do the gating. 

ONE POTENTIAL FAILURE MECHANISM

If we first posit that a register has the typed character code at the end of the XIO Write instruction, and that nothing in the execution of the I1 and E1 steps of the XIO Sense DSW make use of that hypothetical register, then if the register clearing pulse does not get to the register, we might get the symptoms I observe where any bits from the typed character code remain on in the destination register. 

REVIEWING PATH OF DSW DATA FROM CONTROLLER TO ACCUMULATOR REGISTER

During execution of an XIO Sense DSW, at the start of the E2 step of execution, the typewriter controller logic turns on bits that should be a 1 in the DSW. It does not turn off any bits - again, the circuits in the 1130 generally are asymmetrical and flip bits on with edge sensitive gates. While the controller holds the desired bits at 1, pulling them to logic low since the IO Bus is inverted, an early step of E2 for the instruction gates the IO Bus to the B Bus. Assuming the B bus was cleared previously then it has 1 bits only in the positions that were set in the IO Bus.

A bit later in the E2 step of the instruction, it gates data from the B register to the D register. If the D register was previously cleared then it will match the B register value. A touch after the transfer, control lines are set to the arithmetic logical unit to cause the value in the D register to be transferred into the A (Accumulator) register. 

TRYING TO FIND A FAILURE MECHANISM THAT INVOLVES THE D REGISTER

We know that the B register updated after every memory access, so that the original typed character code from the XIO Write instruction is replaced, first by the XIO Sense DSW instruction itself, then by word 2 of the IOCC in step E1, and finally from gating of the IO Bus in step E2. 

However, fetching instructions and reading the IOCC does not involve the D and A registers, only the B register. Thus there is the potential that something has gone wrong with clearing one or both of them, so that when the IO Bus is gated into D we are just doing an OR of the IO bus with the prior contents of D. 

For this to happen, we must have the character code of the XIO Write instruction somehow get transferred to the D register. There is no need for this to happen as the XIO Write should simply have the data in the B register so the typewriter controller can work with. I must find evidence that a transfer takes place to D otherwise this explanation of the defect can't be correct. 

Looking at the logic of the machine, the data should stop at the B register because the CCC counter is decremented to 0 at the start of step E3 of the XIO Write instruction. The last thing in the D and A registers will be the first word of the IOCC as it was read in step E2. For this speculation to cause the symptoms we see, the transfer into D must happen in E3 of the XIO Write, through some kind of defect. Then, a second defect must suppress the clearing of register D so that when the XIO Sense DSW step E2 gates in the IO Bus, we get an OR with the prior contents of D.

I am skeptical that I would have two scattered defects that combine in this way but otherwise code seems to run fine on the 1130 system. I need a starting hypothesis to debug the machine, otherwise I might need to monitor hundreds of signals blindly to try to spot a problem. More thought is required.