Working with RTE IV BI am still unable to get RTE under the HP1000 simulator to talk over more than one terminal at a time. I am poring over every word in all the HP manuals - system generation, online generation, user reference, and so forth - hoping to find some clue to why I am not seeing a prompt on the second terminal.
Since I have the loaner 12966A BACI card, I stuck it into my system to verify a few things. First, it illustrated that this card does not jam up I/O like my defective one. Second, it showed that I could bring up RTE with both cards installed. Third, it let me try to use my second terminal.
Oh frabjous day!
The card worked fine, my RTE came up and I could simultaneously run sessions on both of my terminals! I still don't know why I can't get the HP2100 simulator to work properly, but now that I know the systems I generate will work properly on real hardware, I am more than satisfied.
Diagnosing bad 12966A BACI card
To properly load down each output pin, I will need a 1.5K resistor tied to -2V. That also means I need an added voltage source of -2V and extra clips to place it into circuit. However, I could do some initial testing and found several output pins high.
However, I believe this is because the card thinks it is selected. When the signals SCL, SCH and IOG are all high, it enables all sorts of outputs to report status, request interrupts etc. The input pins are open, thus the state of the selection logic is indeterminate.
To resolve this, I grounded the three input signals at their pins, then examined the condition of the NAND and inverter gates which create the selection signal for everything else. Armed with chip locations and pin numbers, I set out to check the operation of those two selection gates.
They worked properly. With the inputs unconnected, the resistor networks that normally pull these down with a -2V bias instead allow the inputs to float high, driving the NAND gate to a logical 0 and that is inverted properly by the inverter to logical 1. Grounding any of the input pins will drive the NAND gate to 1 and that gets inverted to 0.
Next I tried applying the -2V bias voltage to the board and checking the resulting open pin voltages for the selection signals as well as the output of the NAND gate. This should make every input a 0 whereas right now they all appear as 1.
All the inputs were indeed logical 0 and all the outputs were correctly logical 0 as well, so any problem I have is not on the edges (inputs and outputs). Instead it is something in the interior logic, for example some gate that disregards the selected signal and emits output at the wrong time. This will take a bit more time to debug.