Creating my first testbed - transfer of virtual address in Linux to the FPGA side

BUILDING MY MINIMAL TEST SYSTEM TO PROVE OUT A FEW KEY CAPABILITIES

My first cut at this is a simple SOC where I set up the HPS to FPGA Lightweight (LW) bridge as well as the FPGA to HPS (F2H) bridge. The intent is to pass one message over the LW bridge giving the FPGA a virtual address of a given word in the Linux system. I will use the LEDs and slide switches on the board to display the address latched into the FPGA, which I can compare to the address I write out of the UART port from the Linux image in the HPS side. 

If this works, a quick evolution of this will make use of the F2H bridge to fetch the word from the memory of the Linux image and latch it, using the address latched by the LW bridge. I can then compare it to be certain that I have the ability to read and write memory in Linux from the FPGA logic.

Assuming both of those work, I can use the same testbench with new programming in the Linux image to open a file, memory map it and pass along the address of the first word to my FPGA for display. The linux side will mmap() the file and prepopulate it, since I don't want to have page faults slowing down response when the FPGA is actively reading or writing sectors in the virtual 2315 cartridge file which is the ultimate purpose of these transfer mechanisms. 

CONFIGURED THE SOC AND BRIDGES PROPERLY

I was able to set up the SOC with the Linux (HPS) side implementing two of the three possible bridges - the lightweight link from HPS to FPGA side and the full FPA to HPS link. These expose the two memory mapped Avalon interfaces to my FPGA logic. The top level wrapper links all the board pins to the proper hardware and connects the SOC to either the pins or my logic to control all those signals. 

Configuration of my SOC

The visual connections from Qsys are visible in the diagram above along with the names of the signals exported from the SOC out to my FPGA logic. It also shows the address range of the two bridges, with the FPGA to HPS (F2H) bridge able to generate any 32 bit address but the lightweight HPS to FPGA (LW) bridge only addressing x00000000 to x00003FFF 

WRITING MY LOGIC IN FPGA TO OPERATE THE INTERFACES

Next up I have to code logic in my FPGA which implements the appropriate Avalon Memory Mapped interface which is how you drive the bridges. I will begin with an static idle set of signals for the F2H bridge as I will only be receiving transactions from the LW bridge in the first version of this project.

That logic will capture a single word sent over the bridge to location 00000000 which will be the virtual memory address from the Linux side. We latch that and have it available for display on the LEDs of the board. 

Since the board only has eight LEDs but the address is 32 bits, we will use the slide switches to select which of the four bytes are visible. I begin operation with all bits on in the latched register, but expect a different value to be sent from my Linux code.

LINUX SIDE CODE NEEDED

In addition to the HDL there is a very tiny program that must execute in the Linux image to drive the other side of the LW bridge. It must first activate that bridge by writing control values to some bridge control registers, selecting a specific address defined by the Cyclone V chip. It can then drive one write transaction over the bridge to the FPGA side, passing a virtual address which it also writes on the serial port for my confirmation.