Finished verification of write data capture logic

ADDED ADDITIONAL THREE BIT CELLS OF ZERO

Since my testbench reads lines from a text file that are twenty bits long, my testing has had a preamble length that is an exact multiple of 20 bit times, but it is more likely in the real world that we have a different number that isn't zero modulo 20. 

I added three extra bit cells with data value 0 at the beginning of the simulation. The logic worked just fine, syncing properly solely based on a long string of 0 bits followed by a sequence 1 1 1 1 0 that represents the sync word. 

TESTED SHUTOFF OF WRITEGATE EARLY IN SECTOR

I first set the de-assertion of WriteGate at a random point in word 267 of a sector. The result was that the capture of that word was abandoned and the partial word was NOT captured to RAM. 

I then adjusted the drop to exactly the point after it had completed a word and put it to RAM, 

TESTED DELAYED SWITCHON OF WRITEGATE

This test assumes that for some reason the WriteGate is not turned on at the proper time at the start of a sector. This also delays the start of the clock phase A and phase B signals. I set up the start of this behavior at about 2 ms into the 10 millisecond sector time. The result on a real system is that the sector will extend past the start of the next sector which would corrupt that next sector. 

Indeed, with this test setup we were in the midst of writing word 268 when the Sector Mark starting the following sector (3) dropped, thus we did see the situation expected.

TESTED MALFORMED SYNC WORD BEHAVIOR

I wanted to verify that if we see any 1 bits in the stream before we read a valid sync word, we will react accordingly. That worked properly as well, locking the drive into the error condition where it would take a power cycle to resume operation. 

DISK MODELING MODULE IS CONSIDERED VERIFIED

Based on all the testing I could accomplish via simulation, the disk modeling side of the project is working as expected and ready for live testing on the IBM 1130. Time to move on to the logic that interfaces with the bridge for communication between the FPGA side and the ARM/Linux (HPS) side of the board.