Linux side test set up

ADDITIONAL TOOLCHAIN FOR THE HPS SIDE - WENT FOR SAME BACK LEVEL 17.0

The Intel System on a Chip Embedded Design Studio is a bit toolchain that does the compiling and building of the software which will run in the Linux image on the ARM processors in the HPS side. I loaded the same level as my Quartus tools, 17.0, which is as close as I could come to the version 16.0 used to create the Terasic demonstrations. 

STARTING A SIMPLE C PROGRAM TO SEND VIRTUAL ADDRESS AND ECHO CONTENTS

The first step of this process is to create the appropriate header file. The Intel toolchain comes with a program that reads the detailed SOC description I created with Qsys and produces a header file for use with C programs. 

Alas the scripts to run this are not working correctly out of the box. Not a surprise given the generally shoddy nature of toolchains, but something I will need to fix before I can whip up the relatively simple program. 

The means of accessing the bridges and other hardware elements attached to the Linux processor on the HPS side is through memory mapping. These all have addresses within the 32 bit virtual space that you access to control the hardware.

GPV registers activate and control the three bridges between the HPS and FPGA sides - thus the first step is to point to the proper location and store a magic value activating the bridge. Then the actual writing through the bridge involves similar stores to locations in memory, so that I can send the correct data over to my FPGA logic.

These magic addresses are based on address arithmetic from various header constants thus I need the header to be right before I can make much headway.

MEANWHILE SLOGGING THROUIGH THE SOC/FPGA SIDE

All my code synthesized just fine but I began to encounter errors with the fit and route functions of instantiating the design for the FPGA. This seemed to be because Quartus didn't have enough information about some of the hardware connections. 

I realized that the TCL scripts although named for the SDRAM function I am not including in my system, do provide some pin assignment and parameters that are essential to properly building the system. 

After running this, the build completed successfully. I have an FPGA bitstream that should set up the FPGA side to communicate with the HPS side and my program over there.