Workflow for the Intel/Altera based Terasic DE10-Nano board

SET UP PINS AND OTHER DETAILS USING TERASIC SUPPLIED APPLICATION

The Terasic DE10-Nano board has a Cyclone V System on a Chip (SOC) chip along with quite a few peripheral chips providing functions like DRAM, HDMI video, USB and the like. The Quartus toolchain is fully generic for anyone who makes use of the Altera/Intel FPGA or SOC chips, including this one, but is unaware of how various product and board makers have packaged the chip with other components.

Terasic offers a System Builder tool that configures the high level HDL file and the settings file appropriate to their DE10-Nano board. The user selects checkboxes for particular components or functions on the board and those are included or excluded, generating a project based on any subset they choose of the board's capability. 

The settings file for Quartus has all the important configuration information - which pins of the SOC are connected to various devices or external connectors on the DE10-Nano board, what direction and IO parameters it uses, plus other details that will customize the project to this specific board. 

USE QUARTUS TOOLCHAIN FOR SUBSEQUENT DEVELOPMENT

The output of the System Builder is the start for our Quartus project, where we continue the development and ultimately load the functionality into both FPGA and HPS sides of the chip. Starting from this point, we first configure the SOC chip itself using the QSYS tool inside Quartus. 

With that done, my user logic coded in HDL files are added to the project to complete the FPGA side programming. Any code that has to run on the HPS side, for example within Linux, is also produced by this toolchain, compiled and introduced into the Linux image sitting on the SD card on the DE10-Nano board. 

The programmer tool can load the FPGA or our Linux image can load the FPGA side after Linux boots up. 

I will go through details of each step as I proceed, in future blog posts.