A few hours invested to get the disk simulated signals working on testbench

BIZARRE BEHAVIOR OF THE VIVADO SIMULATOR REQUIRED EXPERIMENTATION

In Verilog, you specify delays between signal changes using #nnnnn to specify how many units of time 'n' to delay before taking the next action. The sector pulses occur 5 milliseconds apart and last for 165 microseconds duration as an inverted logic signal. The repeating process in the testbench to generate this was written as:

 forever begin
       BUS_SECTOR_DRIVE_L <= 1'b0;
       #165000000
       BUS_SECTOR_DRIVE_L <= 1'b1;
       #4835000000
       BUS_SECTOR_DRIVE_L <= 1'b0;
 end

What I was finding was 165 us for the 0 portion but only about 500 us for the 1 portion, far from what I intended. It acted as if it simply lopped off the 483 from the beginning of the delay value. 

I resolved this by repeating a smaller delay value and the same signal value to add up to the desired total delay:

    forever begin
       BUS_SECTOR_DRIVE_L <= 1'b0;
       #165000000
       BUS_SECTOR_DRIVE_L <= 1'b1;
       #500000000
       BUS_SECTOR_DRIVE_L <= 1'b1;
       #500000000
       BUS_SECTOR_DRIVE_L <= 1'b1;
       #500000000
         . . .

 This worked properly. I would expect that if a value is too large for the simulator to handle, it would issue some kind of error message to warn me, rather than silently failing and doing so in a way that appears to be a random value. 

EXTENSIVE WAIT TIMES FOR SIMULATION TO MODEL ONE ROTATION OF THE DISK

The drive spins at 1500 RPM, taking 40 milliseconds to turn once. With the 500,000 to 1 time simulating each picosecond, this would chew away on my laptop for five and a half hours. Just a single sector, the minimum to watch the logic archive content to RAM, will require one hour and almost forty minutes. 

See one mistake or make one refinement, the cycle time is about two hours. Very tedious.