Code written and simulated for FPGA in new 1130 MRAM core memory replacement design

ROLE OF THE FPGA

The FPGA produces all the control signals that drive the other chips on the PCB. I can update the FPGA and modify the control signal behaviors without having to create new versions of the PCB. 

The Magnetic Random Access Memory (MRAM) chip has three control signals that are used to cause it to read the contents of the currently addressed word and put the bits on the data bus or to write the values on the data bus into the currently addressed word. These are the E, W and G pins which are active low and must conform to timing specifications and sequences defined for the MRAM chip. 

The MRAM data bus is bidirectional, either outputting the value read from memory or accepting new data to write into a memory location. The control pin G sets the data bus to output the data values. Data that we want to write into the MRAM chip, coming into the PCB from the 1130 Storage Buffer Register (SBR), has to be driven onto the data bus, but not when the MRAM is generating the bits while signal G is active. A Gate control signal is used to control a buffer chip, so that it is either high impedance or driving the SBR bit values into the MRAM data bus. 

During a read cycle, after the MRAM has put the memory word on the data bus, output chips can pull the 1130 Sense lines low to set an internal 1130 register bit to 1. They will only do this if the bit value on the MRAM data bus is a 1, and only when a control signal allows the output to occur. Testing prior versions of the PCB has exposed issues where the output bits work well if the total number of 1 bits in a word is small, but above a certain number of 1 bit values, the word is not correctly stored in the 1130. 

To help with this, the FPGA has individual control signals for all 16 data bits and the two parity bits for the word to be output. My first version of the FPGA logic will turn on control signals for three bits at a time, skewing the transfer of the word value into the 1130 across six clock cycles of the FPGA - each cycle being approximately 83 nanoseconds long. I could changes this to nine cycles of two bits each, or some other combination. However since a read cycle is only 1.6 microseconds long, trying to put each of the 18 bit values in its own clock cycle would take almost the entire read cycle. 

Since the 1130 control signals such as +Storage Read are asynchronous to the FPGA clock, I have to use a chain of flipflops to synchronize and protect against metastable issues. That adds up to four clock cycles before the logic recognizes a read and begin emitting control signals. We also need a cycle or two to make the MRAM read before it places the data values on the data bus of the chip. Adding all those up, a read with all 18 bits on their own clock cycle would take 2 microseconds, exceeding the window of time available for the 1130. 

VERILOG WRITTEN AND SIMULATED

I created the logic for the FPGA using the Verilog language. It monitors the hardware reset signal I generate from the PCB, then watches the 1130 for the control signals +Storage Use, +Storage Read and +Storage Write. Based on those signals, it produces the control signals for the rest of the PCB. 

I wrote a testbench and simulated the logic for the FPGA. I verified that it produced reasonable sequences of the control sequences, with correct durations, which should correctly read and write to the  MRAM chip on the PCB. I also saw that the pulses into the 1130 when a word is read are skewed in groups of three bits, to limit the total current flowing across the cables at any instant. 

BITSTREAM GENERATED TO LOAD IN DIGILENT CMOD S7 FPGA BOARD

I synthesized the logic and created a bitstream. This will be downloaded into the Digilent CMOD S7 board, placed in an onboard memory, and used to configure the FPGA on powerup. I expect the FPGA board to arrive during the week and will set up that board with the bitstream. 

WAITING ON THE NEW PCB THAT EMPLOYS THE FPGA

JCLPCB.com is busy building my four layer printed circuit board for the revision of my 1130 MRAM which is a PCB that plugs into an IBM 1130 in place of an entire core memory compartment. I hope to receive the new board as well as some addition components from Digikey by the end of the week or early in the following week. 

The CMOD S7 board fits in the lower left of the PCB in the image above. The MRAM chip is right in the middle of the PCB and the three cable connectors are across the top of the board. 

Testing 1130 MRAM board - defect in design identified

LOCATION ZERO IS SET TO VALUE OF ZERO DURING A SYSTEM RESET

I saw two categories of problems while testing the memory board, now that I have the system power more reliable (but not still fully fixed). First, when more than a few bits are set to 1 values, the data does not seem to be reliably read back into the Storage Buffer Register (SBR). Second, many times when I hold down the Reset button (or at power on reset), the contents of location zero is set to all zero bits. 

I dug into the timing of various signals when the machine comes out of reset and to find vulnerabilities that will result in a spurious write being commanded of the MRAM chip. The logic for controlling the lines +Storage Use, +Storage Select, +Storage Write and +Storage Read produce unexpected values as a reset condition is release, which triggers my board to perform a write operation. 

+Storage Use will be on at any time except for a storage cycle when the 1130 does not want to access memory, thus it is on immediately as reset is released. +Storage Write is on immediately after reset is released and also during the entire time that reset is active. 

It is even possible that this flaw in the design could cause problems at other times while the system is running, but in any case it must be corrected. 

REFINING THE USE OF CONTROL SIGNALS BY MY BOARD

In systems using the faster 2.2 microsecond core memory type, the signal +Storage Select will emit a short pulse when the processor steps into states T0, X0, T4 or X4, which will trigger a storage cycle as long as +Storage Use is also high. In normal processor execution, each storage cycle takes eight T clock steps, T0 through T7. The first half of the storage cycle, T0 to T3, is when +Storage Read is high. The last half is when +Storage Write is high. Thus the IBM core memory logic is triggered by the pulse as long as +Storage Use is high, but does a read or a write based on whether +Storage Read or +Storage Write is high. 

In the 3.6 microsecond memory type, such as the machine into which my board will be installed, +Storage Select is driven by the high address bits to select which core memory compartment is active. In the machine I am restoring, there is only one gate so this is effectively always on. In fact, the core memory logic in that compartment does not even look at a +Storage Select signal since memory in gate B compartment C1 is ONLY used with 4K or 8K configurations of 3.6 uS core. 

MAJOR PIVOT IN DESIGN OF THE BOARD

I decided to ditch the timer modules and instead depend on a small FPGA to handle the timing. I designed around the Digilent CMOD S7, a Spartan 7 board. It has enough input-output pins to make the operation of the board fully flexible. I did have to add a 5V power supply regulator to feed the CMOD. 

Now, the pulse to write a 1 into the Storage Buffer Register (SBR) for each of the 16 data and 2 parity bits is an individual line for each bit. Since the existing board works okay for a small number of 1 bits but fails with larger groups like 6 or more, having individual control would allow me to stagger the pulses across the bits so that any funny analog issues that arise from the simultaneous activation are avoided. 

I also control the individual control signals for the MRAM chip - Write, Data Out and Enable - so that I can refine the timing of the activation if needed. Even the buffer chips which block the incoming SBR bits from the memory during reads but pass them through on writes is controlled by the FPGA. 

This definitely requires a change and a new PCB to be fabricated. I also have to write the Verilog for the FPGA, but that is dead simple for this case. While the board is being manufactured, I can write and test the code. Then, when testing, I can adjust timing of signals to refine the behavior of the board.

Slowly improving ability to use LTspice to model circuits with germanium components

WHY MODEL AND HOW

LTspice is a free version of the SPICE circuit modeling software. Entering a schematic allows the operation to be simulated and graphs to be produced of the voltage and current at selected nodes. Very valuable to understand the operation of a circuit in detail. I also find it useful to modify components to see how they would behave if they are defective, in order to confirm a hypothesis about which part has failed. 

The libraries provided by Analog Devices when you download LTspice include many component, but not every possible part. Usually the Spice model for a component can be found online and added to your schematic. However, there are almost no models online for Germanium transistors and diodes.

IBM USED GERMANIUM SEMICONDUCTORS IN THE SMS AND SLT PRODUCT FAMILIES

Standard Modular System (SMS) was the basis for IBM's transistorized computers in the 1950s and early 1960s. Solid Logic Technology (SLT) as the basis for the 1960s and 1970s computers such as S/360 and 1130. The diodes and transistors used in both families were Germanium based. 

While the industry was transitioning to Silicon semiconductors which are much better for most purposes, IBM needed massive quantities of transistors and diodes, including manufacturing their own. Staying with Germanium assured them of adequate supply and avoided the need to re-engineer many circuits. Similarly the industry was beginning to use integrated circuits (ICs) in the 1960s but IBM's volume needs and other factors led them to stay with discrete transistors and diodes in the SLT generation. 

IBM used many different transistor types in their products in SMS. In SLT, the transistors and diodes used in the SLT modules were much more standardized but SLT cards often included separate transistors in a myriad of types. 

SPICE MODELS FOR GERMANIUM SEMICONDUCTOR COMPONENTS

There are only a handful of models to be found on the Internet for Germanium transistors. Music effect pedals make use of Germanium because of the way that signals are distorted by the device's characterists - pedals such as a Fuzz box - which is by far the largest use of Germanium today. Thus, the few transistors that are used in effect pedals do have some models to be found. 

However, there were many hundreds of different Germanium transistors sold, the vast majority of which have no models online. IBM made use of almost 200 transistor types for SMS and SLT. This is where my problem lies.

GERMANIUM VERSUS SILICON GROSS BEHAVIOR DIFFERENCES

Silicon semiconductors tend to have a turn-on voltage across the base-emitter junction of around 0.6V while Germanium semiconductors turn on at much lower levels. typically 0.1 to 0.3V. The operation of a transistor with a given voltage at the base can be very different between Germanium and Silicon, as a consequence. 

Germanium transistors operated in reverse mode (switching the emitter and collector) work better than Silicon transistors in the same mode. The amplification factor (beta) is less in reverse mode, but at a reasonable level with Germanium. Other characteristics worse for both types in reverse mode, but there are some circuits (especially effects pedals) that chose to use the transistor in reverse mode. 

Germanium devices have higher leakage currents and are less stable under temperature variations than Silicon. They also are more susceptible to failure due to air leaking into the package than Silicon. Silicon forms an insulating oxide when exposed to air, which limits the impact on the device, while Germanium does not. Finally, the way that the component leads enter the typical Germanium package were susceptible to breaking or corrosion forming at the entry point. 

IBM labeled their transistors and diodes with their own designator, even if the part was procured from an industry source who sold the same part with an industry recognized number. Thus even if a model had existed for a particular transistor under its commonly known number, to model an IBM circuit required knowledge of the IBM to industry standard number translation. 

GRADUALLY EXPERIMENTING WITH SPICE MODELS FOR SOME IBM CIRCUITS

I have been hacking at some models that exist for Germanium devices, trying to get the IBM circuit to operate as it should. I have found a table that circulated among IBM repair people (Field Engineers - FEs) during the SMS era that purports to list industry standard transistors that could be substituted for an IBM numbered transistor in a pinch. These may list five or six different transistors, thus making clear that the substitute is NOT an exact match. 

I have located some spec sheets for the industry standard transistors in that substitution table and from that I have worked up a potential set of specifications for the IBM part, such as hFE and Vceo, that would be the basis for a spice model of that IBM part. This is challenging because a spice model does not have entries like hFE, but instead has a myriad of parameters as you can see below:

My challenge is to turn the potential specifications I derived such as hFE into the parameters above. This is a work in progress. It will be quite valuable in the long run to be able to model IBM circuits accurately. 

Replacing parts on 6V regulator SMS card to resolve 1130 power issues - part 2

TESTING TRANSISTORS WITH CURVE TRACER

I unsoldered all the transistors from the board so that I could put them on the curve tracer to verify whether the transistor was working properly. There are two 026, an 086, a 123 and a 108 transistor that I removed. I have ready replacements for some but I don't have a spare 123. 

Originally the failure occurred after the regulator has been operating for a while, was powered down, and then power applied again within a minute or two. That may mean that when the transistor heats up its behavior changes, so I will apply some heat and cold air while testing the transistors. 

I tested the 123 and 086, which seemed to behave properly and were not so sensitive to heat or cold that they misbehaved. I unmounted the 108 transistor from the heat sink and found it to be quite flakey on the curve tracer. 

REPLACING SUSPECT TRANSISTOR

I used a spare 108 that I owned to replace the bad one. In addition to the spare I used, I had bought a large set of 108 transistors from eBay years ago. When I began testing them, I found wildly different amplification ratios (beta) among them, no two the same. I wonder if these were simply printed with 108 and sold as rare transistors, but are actually various PNP parts of a different type. Counterfeit integrated circuits are a widespread problem, but perhaps I blundered into some counterfeit transistors. 

RESULTS OF POWER CYCLING

The machine was much better, so much so that I had begun to believe the problem had been fully resolved. However, I did manage to get it to fail in the same way - oscillations around 3V - it just took more to force the problem. Drat. 

POSSIBLE NEXT STEPS

I can test the two 026 transistors, since I do have spares to use. I did pull the two diodes and test them, which also let me determine that an IBM DY diode is a 3V Zener. 

I could also test the six 108 transistors in the rest of the regulator, which might be the failing component somehow. 

Replacing parts on 6V regulator SMS card to resolve 1130 power issues - part 1

REPLACING ALL RESISTORS

My package from Digikey finally arrived after the fulfillment delays and then the snowstorm related delivery service delays. The next day I went to the workshop to swap in all the replacement resistors. These were the parts that had deviated from their nominal values which might have contributed to the misbehavior of the regulator. 

INTERMITTENT FAILURE CONVERTED TO STEADY FAILURE

With the parts changed, the regulator now enters the same state that it only did on a repower before - where the output is down around 3V with oscillations, ballooning the current into the regulator required to drop 15V to 3V, resulting the the circuit breaker tripping. Previously the machine would power up fine when cold, run for a while, then if it were powered back up after only a few minutes powered down, this state would occur.

I choose to believe this is progress. A steady failure can be investigated and the root cause found. I have been trying to recreate the failure behavior by shorting or opening various components under LTspice but have not yet been successful. I will begin to remove the transistors and put them on the curve tracer so that I can spot any obviously defective such part. 

Deconstructing the +6V regulator SMS card schematic to isolate functions

DIGIKEY IS SLOW TO FILL MY PARTS ORDER DUE TO HEAVY VOLUME

As the parts have not yet been shipped, they will not arrive by midweek as I had expected. I took the time to document the regulator and explain some of its function.

REGULATOR HAS AN SMS CARD TO REGULATE THE VOLTAGE PLUS OTHER PARTS

The regulator has six IBM type 108 germanium power transistors each on a large heat sink, a circuit breaker, a few other parts and then two SMS cards. One card simply detects when the output voltage is above a trigger threshold, so that it can short the output to cause the circuit breaker to trip. The other is the logic that drives the six power transistors so that the current they are passing will produce a 6V voltage drop over the load. 

The schematic for the regulator includes all the above parts. In addition, it is drawn with the IBM conventions where they show electron flow from the top to the bottom, upside down from the usual orientation in drawing circuits that considers current to flow from positive to negative. IBM also draws transistors in a non-standard way. 

DIFFERENTIAL/COMPARATOR PORTION OF THE CIRCUIT

The two transistors above have their emitters connected through an emitter resistor. This biases the voltage needed on the base of the transistor to cause it to conduct - the more current through the pair of transistors, the higher the voltage drop on R5 which means that the base needs to be more negative to enter the conduction region. 

The right transistor feeds a bias current to the power transistor driver, based on the voltage seen across the output terminals of the regulator. It is trimmed by a potentiometer to produce the 6V voltage drop on the load. The left transistor drives the amplifier based on a fixed voltage from a Zener diode.

If the voltage across the output dips below 6V, the right transistor has less current flow or cuts off, lowering the total current through the emitter resistor R5. This causes the left transistor to conduct more heavily. The left transistor current is amplified and drives the power transistors to increase current leading to restoration of the output voltage. 

If the voltage across the load bumps over 6V, the right transistor conducts more heavily, which increases the emitter resistor R5 voltage drop. That lowers the conduction of the left transistor, the amplifier has a lower output and therefore the power transistors lower the current to the load until the voltage drop restores to 6V. 

AMPLIFIER PORTION OF THE CIRCUIT

The differential circuit left transistor output current is fed into the base of transistor T3. As the differential circuit requests more power, transistor T3 conducts more heavily. Its output feeds the base of transistor T4, adding further gain. T4 delivers more current from the - input rail to the base of transistor T6, again being amplified to pass current from the - rail to the bases of the six power transistors. 

POWER PORTION OF THE CIRCUIT

Six IBM type 108 transistors operate in parallel to deliver the current requirements of this regulator. It is capable of delivering 24A across the load. The transistors have emitter resistors that cause these to balance the load across the six. As a transistor delivers more current, the voltage drop on its emitter resistor rises so that the voltage difference at the base lowers to decrease conduction. 

OVERVOLTAGE PROTECTION CARD

A differential pair of transistors T2 and T3 compare the fixed voltage of a Zener diode on the left with a fraction of the actual output voltage delivered to the right transistor through an adjustable potentiometer. When the voltage on the right transistor gets high enough, the right transistor conducts enough to reach the trigger voltage level for the silicon controlled rectifier (SCR) SCR4. Once triggered the SCR stays in conduction until power is removed. As SCR4 conducts, it delivers the trigger voltage to SCR46, which shorts the entire output of the regulator. 

This circuit will force the circuit breaker to trip on the regulator. It fires in a few tens of microseconds, protecting the logic components in the 1130 from damage if the voltage is too high. The potentiometer is set to a protective target, e.g. 6.8V, where the card will cut off the output voltage. 

Further dive into the 6V regulator circuit breaker spurious tripping

SET SCOPE TO TRIGGER IF REGULATOR OUTPUT HITS 6.7 OR HIGHER

I hooked the oscilloscope up to the 6V output of the regulator and set the trigger to a level of 6.7V so that I would see whether a high level is the cause of the spurious tripping of the circuit breaker. The overvoltage protection card will trip in a few tens of microseconds if the voltage is above the 6.8V trigger level I had set. 

The system tripped immediately, so I isolated the logic from the regulator and then watched the voltage on the output without the overvoltage protection card installed. It zoomed up to 15V and stayed there. I pulled the regulator card out and found a solder bridge defect where I had removed and replaced a couple of parts. After removing the solder bridge, the regulator worked properly and generated 6V. I hooked the logic back up.

The observed voltage completely dashes the theory that the breaker is tripping due to an overvoltage condition detected by the overvoltage protection card which clamps the output to zero. What I am seeing instead is that when I power down for a short interval and then power back up, the voltage comes up to about 3V and oscillates around that level, leading to excessive current draw which trips the breaker.

POTENTIAL CAUSES

It is possible that some parts out in the 1130 logic are producing a short circuit under the repower conditions I am seeing, causing the 24A capacity of the regulator to be unable to deliver 6V. For there to be 3V at the regulator output, the resistance of the load must be about the same as the equivalent series resistance of the regulator. 

The regulator has a 0.072 ohm 90W resistor that all power must flow through. If that were the ESR, just to make a simplifying assumption, then the resistance out to the short would have to be roughly the same. to create a voltage divider. That resistance is equivalent to more than 50 feet of 12 gauge solid wire, while the size of the 1130 and its use of stranded wire make this very unlikely to be the cause.

The other area of suspicion is that this is a defect in the regulator. That is either caused by out of spec parts values or a defective semiconductor device. 

I have ordered a complete set of replacement resistors to bring all the values in line with the design. I should be replacing them midweek and testing again. If the problem persists, I have seven semiconductor parts that may be at fault. Intermittent contacts in the germanium transistors or oxidation defects on the transistor could be occurring, although why that will happen only in the repower scenario is a mystery. The same is true for a zener diode and a regular diode that are part of the comparator on the card. 

The failure scenario involves the regulator driving insufficient current to produce 6V across the load. That may be a clue to the part of the regulator circuit that is failing in the repower situation. However, it could be due to a number of different parts malfunctioning or being off value. 

The regulator has six germanium power transistors (IBM 108 transistor type) in parallel to deliver the current needed for a 6V output. The six power transistors have their base junctions driven by another 108 germanium power transistor mounted on the regulator's SMS card. If we call this the drive transistor, then its delivered current is controlled by a cascade of two smaller transistors, a type 086 controlling a type 123 that feeds the base of the driver 108 transistor. 

The regulator heart is a pair of type 026 transistors set up as a differential amplifier with a shared emitter resistor. One transistor is driven by the output voltage, using an adjustable resistor to fine tune the target voltage. The other transistor is set with a Zener diode to a fixed reference voltage. As the actual voltage rises above or falls below the target, current through one of the 026 transistors moves to decrease or increase the current into the 086 transistor. That lowers or raises the current through the 123, the driver 108 and then the six power 108 transistors, restoring the output voltage to the target. 

Ordered new components for 6V regulator SMS card for IBM 1130

REPLACING ALL RESISTORS

I found a few with significant drift but most were off nominal enough to warrant my replacing all of them. I ordered the correct parts from Digikey and should have them early next week to swap onto the board. In the interim, I will put the card together with its existing parts and do some other debugging of the issue where the regulator's circuit breaker trips on power-up if the system had been on for a while and only recently powered down. 

Dealing with power supply breaker trips in IBM 1130 6V regulator

BACK AFTER EXTENDED TIME AWAY

My wife planned a big party for my 75th birthday that involved significant planning and setup in advance. Just prior I was down with a long viral infection - not flu nor covid, just a mystery ailment circulating in the area - then a nasty cold struck right afterwards. Add in quite a few other obligations and visits and the result was a long period when I was away from the workshop. Happily I am now back.

SPURIOUS CB TRIPS IN 6V REGULATOR

For some time the 1130 would trip the breaker on the 6V regulator when powering back on after the machine had been off for short periods. I also saw some random shutdowns while operating. I had found a weak circuit breaker and replaced it previously, but the issues did not go completely away.

A power supply in the 1130 takes the input mains voltage and produces unregulated DC (nominally 13V) from a halfwave rectifier that is then routed to the regulator module which outputs a well regulated 6V to power the SLT logic in the machine. The regulator module has a circuit breaker that protects it from shorts on the 6V rail but also has an over-voltage protection circuit. 

If the voltage goes too far above 6V, this will fire a silicon controlled rectifier (SCR) to put a dead short across the output of the regulator, forcing the breaker to trip. The SCR fires in tens of microseconds, limiting energy delivered to SLT circuitry in an overvoltage situation. The circuit breaker can shut off in a more leisurely timeframe since the output is clamped to zero. 

The regulator module has two SMS cards plugged into it, one that does the regulation and the other that provides the overvoltage protection. 

CHECKING FOR EXCESSIVE CURRENT DRAW

I placed a voltage and current meter on the inputs to the regulator - the unregulated DC coming from the power supply - to see whether the draw was close to the limit of the circuit breaker. If it was operating near its trip point, it might be susceptible to tripping on the power up surge. The 6V regulator is designed for up to 24A supply, but when I monitored the operation it never reached 7A, thus I believe the output of the regulator is safely below the rated capacity. 

One issue I observe is that the unregulated DC input voltage is just over 15V, but the filter capacitors in the power supply for this input have a 15V rating. Further, the documentation lists the nominal value to be 12V, with the actual about 32% above that. 

The power supply has a wiring diagram to support 115, 208 or 230V input power. My workshop is set up for 230V and the wiring is set for that voltage. I have noticed that the unregulated 48V and 12V rails are also running hot by about 10%. Those two are fed from a different transformer that was also wired for 230V. 

The higher input voltage means that the power supply would have to drop more power to achieve a 6V output, however the current is still well below the capacity of the regulator. I am mildly concerned that the voltage is above the capacitor rating. There is some safety margin, but I might want to replace the two filter capacitors with ones with a higher rating. 

The only mechanism I can imagine for the over-voltage from the power supply is if the primary windings have some turns shorted together, so that the turns ratio increases to drive up the secondary voltage. It would require about 20% of the windings to be bypassed to produce the observed voltage. 

The home for this system once I am done with the restoration is in a facility with 208V mains, thus if I leave the wiring as it is, the voltages will be lowered. Nothing I can do in my workshop, however, except to replace the transformer which would be wasteful. 

The transformer has two primary windings that are either put in series or parallel to support the 115, 208 or 230V line voltage. For 208, the jumper you can see from 1 to 5 above would instead be connected between 1 and 4 on TB-1. That reduces the number of windings however since we appear to have too few windings as is, I would leave the jumper at 1 to 5. 

TESTING OVERVOLTAGE SMS CARD

I pulled the SMS card and hooked it to a bench power supply with overcurrent protection. The strategy was to run up the voltage past 6V until I observed the card clamp the output to a short. The card has a 150A SCR acting as the final clamp, although I set my bench supply to trip out at a much lower current. 

The card clamped the voltage at 6.5V, which seemed like a reasonable setting to protect the circuitry and is well above the adjustment of the regulator at just over 6. Since this may be triggering a bit aggressively I altered the potentiometer to increase the voltage where it would fire. 

In comparison the card for the 3V regulator clamps at 3.4V. The same percentage over for the 6V supply would be a trip point at around 6.8V. That is what I set. 

The problem continued. Whatever causes the breaker to trip occurs even with this higher set point. Thus we have a few possibilities left to chase down:

1. Component issues or drifted values on the SLT regulator card cause it to produce a voltage spike above 6.8V as it is powered up with only a short period of downtime (a few minutes or less). 
2. Some component in the SLT logic downstream from the regulator will short when power returns after a short period of downtime but does NOT short in steady use and clears itself after a few minutes waiting before the next power up attempt.
3. Some component on the regulator has an intermittent connection that is opened by the heating of the parts, which works properly when powered but surges on a repower after a brief downtime. 
4. Some defect in the unregulated power supply produces a surge on a repower after a brief downtime that somehow overwhelms the regulator briefly.
5. The replacement circuit breaker I bought on eBay has the same defect as the original part in the regulator, where it heats up inside the breaker during use and makes it susceptible to tripping during a repower. 

TESTING COMPONENTS ON REGULATOR BOARD AND REPLACING DRIFTED PARTS

I began pulling resistors and capacitors from the SMS board and testing them. I found a few that had drifted too far from their nominal value, which I replaced with new parts. I don't have a source for new-old-stock germanium IBM transistors, but do have some parts available on spare parts boards. Thus I could put each diode and transistor on my curve tracer and validate its behavior then replace any that are bad. 

Germanium transistors often failed due to corrosion either where the lead enters the can or on the actual germanium surface. Silicon forms a protective oxide but germanium does not, thus leaks in the can lead to failures in the transistor behavior. A corroded lead might yield intermittent connectivity as heat causes the can to grow during operation. 

Testing fully assembled new 1130 MRAM board - read retriggering solved!

TESTING FULLY ASSEMBLED BOARD ON TEST BENCH

I put the finished board on the bench and tested it by triggering a read (rising edge of +Storage Read signal) and watching the sense output lines. I wanted to see multiple 1 bits being emitted for a given read, with the output lines pulled down to ground for 80-100ns for all the bit positions that have a 1 value. There should be one pulse for those bit positions and no retriggering causing subsequent pulses every 800 ns after the first one. 

Everything looked good with this testing, so I moved on to the 1130. I frankly didn't do a lot of detailed testing on the testbench because it was cumbersome to move the probes around. For example, I didn't try writes nor changing the address bits to verify that different locations preserved their contents independently. 

TESTING FULLY ASSEMBLED BOARD ON 1130

The PCB was connected to the 1130 system and everything was powered up. I used the rotary mode control to set the machine to Display mode, where each push of the Prog Start button will drive a storage cycle - a read followed by a write. That will raise the +Storage Read line at first which is what will allow me to watch the sense output pulses. 

Having first set the mode switch to Load mode, I loaded memory with various values then turned to Display mode. I want to watch the output pulses on selected bit positions, seeing only a single pulse not spuriously retriggered pulses. I also wanted the value latched into the Storage Buffer Register (SBR) to match what I had stored. 

Instead I saw somewhat random bits showing up in the SBR and the scope pattern for the sense output pulses didn't make sense. I was seeing two 80-100 ns pulses, one shortly after +Storage Read went high and then another at the proper time. I didn't see that occurring on the testbench.

FOUND BAD CONNECTION ON WRITE TIMER CHIP

I realized that in most cases, the same data patterns came out for various addresses as I did Display operations. I was not able to store any different data patterns into RAM, but it was returning deterministically (to at least a superficial level of testing). I then discovered a pin on the write timer chain (first of two timer chips) that was not soldered reliably to the pad. After correction, I could write patterns into RAM. 

ORIGINAL RETRIGGERING ISSUE FIXED

I was not seeing any spurious retriggering beyond the duration of the read portion (1.8 uS) of a storage access, which means that the original bedeviling problem has been mastered. It was kind of a stab in the dark to add in the separate transistors to drive the sense output pulses instead of using the open collector logic gate that produced the pulse. 

I then had a eureka moment when seeing the pulses occurring very soon after the start of the +Storage Read high signal. I noticed that a second pulse at the correct time was happening whenever the board was returning  a 1 bit in that position, while the first pulse seemed unrelated. 

EUREKA MOMENT

Realization rolled over me at that moment. I realized that my sense output pulse, which is a transistor pulling a line down to ground for 80=100 nanoseconds, wasn't connected only to the flipflop that would turn on for the falling edge. There were multiple gates connected together in what IBM calls a wired-OR. That is all the output wires from the various gates are just shorted together - with each of them acting as an open collector driver - so that any of them could activate the flipflop. It was not only a sense output from core memory that turns on the flipflop.

What I was seeing was other gates hooked to the flipflop creating a setting pulse for some other reason. The various gates that produce pulses to set the Storage Buffer Register bit position to 1 are:

• IO bit is gated to B register (SBR) - peripheral  controller drives this
• I (Instruction Address Register) is gated to B 
• A (Accumulator Register) is gated to B
• Core sense output pulses sets B

I don't know what would produce one of those pulses during the T0 clock phase of the read cycle, where I was seeing the pulse on the 1130 side. The gates above should only operate if the machine is trying to store something in a memory location - the IAR, Accumulator or an IO controller word - which should not be happening here.

My next round of testing will focus on what is causing this T0 gating to the SBR. I don't understand why this would happen during a Display mode storage cycle. Either this is a defect somewhere in the 1130 that needs correction or it is a normal behavior that does not cause problems when IBM core memory is used. 

These pulses are pulling the input of the flipflop called the "AC trigger" down to ground, discharging a capacitor that was charged up by the enabling line to the AC trigger. If the capacitor is discharged fast enough and for long enough, the flipflop changes state. It requires about 8ma of current sinking to achieve the setting of the flipflop, times each bit position that has it flipflop set. That is up to 18 flipflops (for a word of all 1 bits).

It appears that something occurring during the discharge was being injected back into the 1130 MRAM board through the supposedly open drain NAND chips. Probably a negative excursion of the line which pulled down the VCC of my board enough to cause the ringing and spurious retriggering. The replacement of the NAND chips with an AND followed by a discrete transistor seemed to resolve this as the transistor could handle the short reverse voltages without any interaction with my VCC and ground planes. 

SOME MANUAL OPERATIONS TESTING THE BOARD

Using the LOAD and DISPLAY modes of the 1130, I was able to put in contents to specific locations and read them back. This is a mode where you take a single storage cycle, pushing the Prog Start button to display or load at the current address. These seemed to be working properly.

I then used the STORAGE LOAD and STORAGE DISPLAY switches on the CE (Customer Engineer) panel to load patterns to all memory locations in a loop or to loop through reading all memory locations. Storing a value of x0000 worked correctly, always returning zeroes. However, when I set the pattern to something else, such as xFFFF, the load appeared to be working but when displaying I got back variable random data and parity errors. 

Since parity is generated on my board based on what is read back from the RAM chip, the only way to see a parity error on the 1130 is if the data being latched into the SBR is not what was read from the chip. This suggests a timing issue or another problem that may be happening during continuous successive storage cycles such as the looping of STORAGE LOAD. 

During my next round of testing, I will examine what is happening during continuous storage cycles and look for defects either in my design, the current board or the 1130.