Slow work wiring Signal Conditioner (Sledgehammer) into the disk signals for Virtual 2315 Cartridge Facility

WIRING FIVE SIGNALS THROUGH THE SLEDGEHAMMER

The Signal Conditioner, AKA sledgehammer, will clean up signals coming from the Virtual 2315 Cartridge Facility (V2315CF) through a cable of twisted pair wiring into the logic gates of the IBM 1130. Five of the twenty signal pairs passing through the cable are the priority for conditioning.

These are the -Sector Marker, -Write Clock Phase B, -Read Clock, -Read Data, and -Access Ready signals. The twisted pairs are wrapped with cloth electrical tape to form a cable which runs between the swing out logic gate A of the 1130 processor and the internal 2310 disk drive that fits inside the 1130 cabinet. 

The V2315CF intercepts the signals running over that cable, thus there is a 2310 Interface Board that this cable plugs into rather than into the disk drive. That interface board also has a cable coming from it that plugs into the disk drive. The main unit of the V2315CF will pass certain signals along between 2310 and 1130, but will generate others rather than using the signals coming from the 2310. 

The cable going into logic gate A fits into an SLT card slot in compartment C1. Each SLT card slot is a 2 x 12 set of pins with four of them reserved to carry power and ground for an SLT card. The remaining 20 pins deliver signals into and out of the compartment, in this case between the compartment and the interface board for the V2315CF. The pins on an SLT slot are labeled D02 to D13 for one column and B02 to B13 for the other column. For example, the signal -Read Clock is assigned to D02. 

SIGNAL TONE TRACER NOT USABLE

I tried to use a signal tone tracer, injecting the tone into the signal pin that I wanted to locate, then touching the probe to each wire pair to find the one with the loudest signal. Unfortunately, I couldn't set any level that would let me aurally distinguish the correct pair from the others. Enough tone is coupled through the ground wires that are part of each twisted pair so that every wire pair has almost equal volume. 

VISUAL TRACING FROM CONNECTOR WAS HIT OR MISS

I attempted to spot each wire pair coming from the connector, cutting the signal wire so I could wire in the lines to the Signal Conditioner. About half the time, the wire pair I thought was correct was not and I had to repair the connection by soldering the wire ends and using shrink wrap to insulate the joint. The design of the connector is not conducive to easily spotting the right wire.

Once I do find the proper wire for a signal and cut it, I have to solder on a twisted wire pair segment to each end of the cut. One of the new segments runs to the Signal Conditioner board input, where the signal coming from the V2315CF is injected. The other new segment runs from the Signal Conditioner board to the wire end that is running into the 1130 logic gate. 

When the new twisted wire pair segments are soldered on, their ground wires need to be connected together and to the ground wire of the original cable. The far ends of the new segments get a Molex KK pin crimped on and then they are inserted into five position connectors that fit onto the input and output of the Signal Conditioner board. 

CRIMPING WAS ALSO A PROBLEM AS MY CRIMPING TOOL WAS SUBOPTIMAL

Fastening the pins to small gauge stranded wires with the crimping tool I have in the shop was an exercise in frustration. The tool is not very good, thus the pin would often twist out of position as I attempted the first crimp, or bend one of the tabs outward instead of atop the wire or insulator. Others would appear to be properly crimped but not tight enough to hold the pin on for long. 

I ordered a better crimping tool designed for these pins and able to produce solid connections on the ten pins that are needed for the Signal Conditioner. Once it arrives I will finish up the construction. 

Stumbled upon defect in the Raspberry Pi PICO library routines for SPI links

VIRTUAL 2315 CARTRIDGE FACILITY USES SPI LINK BETWEEN PICO AND FPGA

The heart of the Virtual 2315 Cartridge Facility (V2315CF) is a unit that houses a Lattice Field Programmable Gate Array (FPGA), enough RAM memory to hold one disk's worth of data, and a Raspberry Pi PICO. The PICO mainly manages the user interface while the FPGA mainly implements the disk drive emulation and controls the RAM. 

The PICO implements a Serial Peripheral Interface (SPI) link to the FPGA, with the PICO acting as the master. The PICO exchanges two bytes with the FPGA as a transaction, the first byte having the command from the PICO and the second byte recieves one byte from the FPGA based on that command. 

For example, a transaction code of x88 is a request for the FPGA to return one byte of data from the RAM. The address for memory access was previously transmitted by the PICO as a set of three x05 commands that set the 24 bit RAM address. When the PICO is writing back the contents of a virtual 2315 disk cartridge to the microSD card file that stores the data, it sets the RAM address for each of the 1,624 sectors, reads 642 bytes sequentially from the FPGA and then writes the sector's 321 words of data to the file. 

PICO LIBRARY PROVIDES ROUTINES TO CONTROL THE SPI LINK

Exchanging data over an SPI link is done with a few library calls provided for the PICO. The caller first starts the transaction by asserting the SPI chip select line, then calls the  spi_write_read_blocking function giving it the address of the buffer holding the outbound data to send to the FPGA, the address of a buffer to receive the data coming back from the FPGA, and a count of how many bytes to send. The caller then deasserts the chip select signal. 

The transfer proceeds with the SCLK signal being alternated for the number of bits being transmitted - in this case, that is 16. The MOSI signal sends the bits serially from the PICO to the FPGA. The MISO signal comes from the FPGA and provides the inbound data that is returned to the caller. Thus, an SPI transaction is an exchange. 

The routines that I inherited from the RK-05 Emulator had defined the outbound and inbound buffers as arrays of uint8_t, an eight bit unsigned value (byte). The length of each was 2, since the intent is to exchanges two bytes between master and slave in a transaction. There was also a 2 byte array of uint8_t declared in the routine but never used. 

EXPERIENCED ERRATIC RESULTS AND LOOKED CLOSELY AT THE FUNCTION CALLS

When my logic tried to write back the contents of RAM to the microSD card in the virtual 2315 cartridge, I would get some correct results and some corrupt data returned. I looked for every possible cause and investigated, but wasn't getting anywhere.

The routines that I inherited from the RK-05 Emulator had defined the outbound (OUTBUF) and inbound (INBUF) buffers as arrays of uint8_t, an eight bit unsigned value (byte). The length of each was 2, since the intent is to exchanges two bytes between master and slave in a transaction. There was also a 2 byte array BUF of uint8_t declared in the routine but never used. 

After adding code to verify that the last bits had been exchanged before deasserting the chip select, yet seeing no improvement, I was considering slowing the SPI clock just in case I was getting errors due to hardware signal issues. However, this didn't make sense because at startup the same link transferred 1,624 sectors of data down from the microSD card file to the RAM without a single failure. 

I happened to remove the unused variable BUF from the routines but when I next tested, the corruption rate increased to almost 100%. That was unexpected. 

MY ASSUMPTION WAS THAT THE FUNCTION WAS RETURNING TOO MANY BYTES

Perhaps the issue was the function, which might be overrunning the buffers I passed it. The count was a hard coded integer 2, which should be what controls this completely, but perhaps it was instead returning integers, a longer data type than the uint8_t bytes in the arrays. 

I increased the size of OUTBUF and INBUF to four from two and tried again. The code worked flawlessly. Somehow it was stepping on the stack and causing issues until I added extra room in teh buffers. The code is below. 

uint8_t read_write_spi_register(uint8_t reg, uint8_t data)

{

    uint8_t out_buf [BUF_LEN+2], in_buf [BUF_LEN+2];

    uint8_t buf[2];

    out_buf[0] = reg;

    out_buf[1] = data;

    cs_select();

    spi_write_read_blocking (spi_default, out_buf, in_buf, 2);

    cs_deselect();

    return(in_buf[1]);

}

The cs_select and cs_deselect calls are inline routines:

static inline void cs_select()

{

    asm volatile("nop \n nop \n nop");

    gpio_put(PICO_DEFAULT_SPI_CSN_PIN, 0);  // Active low

    asm volatile("nop \n nop \n nop");

}

I still don't understand what is going wrong but increasing the buffer fixed the problem. This must be why the original programmer left the spurious BUF variable in the routines, something they found solved a problem even if the root cause wasn't understood. 

Testing a write after conditioning the Sector Marker signal for the Virtual 2315 Cartridge Facility

FIXES MADE BEFORE DIAGNOSTIC TESTING RESUMED

The new Signal Conditioner board is in place and ensuring that glitches on the -Sector Marker signal receive by the IBM 1130 logic won't lead to incorrect results. Since that signals looked really good now, I expected everything to work properly now. 

LOGIC ANALYZER SHOWS THAT THE SECTOR MARKER ISSUES ARE GONE!

I recorded the same signals that showed me that doubled edges were caused by the ringing of the signal and led to a spurious termination of the write after only half a sector - 5 milliseconds instead of 10. This time, everything was perfect and the write continued for the full 10 ms. 

The flipflop logic that blocks every other 5ms raw sector marker pulse (+Alt pulse and -Alt pulse) are alternating just as they should, thus the -Sector Marker signal at 5ms is blocked and only the second one is passed through as -4 Sector Pulses and that terminates the write. The probe lead had fallen off the raw sector marker signal, which would have been signal 5 (green) in the trace, but we know the pulse comes at the 5ms point in the write operation. 

ALMOST PERFECT TEST OF WRITE IN VIRTUAL MODE ACHIEVED

This time I did achieve a good capture of the data I wrote to the virtual 2315 cartridge, including the entire sector. I set up a known pattern in a memory buffer in the 1130 and issued an XIO instruction to write to a given sector of the disk (cylinder 0, head 0 and sector 1). I issued an XIO to read in the same sector to a different buffer, confirming that the contents matched what I had written. An offline view of the mini 2315 cartridge using the Showsector.exe program I provided confirmed the content of the sector as well. 

It was not flawless, however, as there was a single bit shift in the data for the last 48 words of the 321 in the sector. If you look at the data from the sector as it was extracted with Showsector.exe, you will see starting at word 0x111 the data was recorded as 0x0224 when it should be 0x0112. Every word from that point forward is the same as the data I tried to write out except for the one bit shift, ending with 0x0282 which was intended to be 0x0141. 

The data that I wrote out was almost the same as in my previous tests, however, words 2 and 3 were changed to 0x2600 in the buffer where they had been 0x0002 and 0x0003 in my original test. Thus I wrote what we see above, at least up to word x111 where things went slightly astray.

I had previously identified that the signal -Write Clock Phase B which comes from the V2315CF into the 1130 might cause this kind of issue. The signal will advance the shift register after each clock. A spurious double edge would cause the register to shift the data by one bit. I had finessed the signal termination to really ameliorate signal issues but they were not ideal. It does appear that we had this one error in about 6,500 clock intervals during the write. That is quite good but not good enough.

The solution is the sledgehammer! One board has five channels of signals that it can process. The -Write Clock Phase B signal is definitely worth slamming into shape, so it is going to be processed. On my next visit to the shop I will be wiring the other four signals I identified so that they pass through the Signal Conditioner board. I don't anticipate any errors after I sledgehammer the signal into shape. 

Testing signal sledgehammer for the Virtual 2315 Cartridge Facility

FILTERING OUT RINGING AND UNDERSHOOT OF SIGNALS

The Virtual 2315 Cartridge Facility (V2315CF) sits in between the internal 2310 disk drive and the IBM 1130 computer's logic gates, either relaying signals between the two end points or generating a signal in place of the one that the disk drive might produce. I found that in virtual mode (disk drive not turned on, the V2315CF simulating it entirely), certain signals exhibit an undershoot to under -3V and quite a bit of ringing, when the nominal voltage levels are +5V and 0. 

The ringing caused the 1130 logic circuits to see the falling edge of the signal as multiple falling edges, thus confusing the logic and creating incorrect results. The path from the V2315CF to the logic gate of the 1130 is complex, with transitions between PCB traces, ribbon cables, more PCB traces, twisted wire cables, additional PCB traces, a pin on a backplane and then wiring in the logic card. There are many impedance transitions and places where signals can be distorted - made worse by a very fast falling edge because of the modern FPGA and logic gates in the V2315CF which switch so quickly. 

SIGNAL SLEDGEHAMMER IMPLEMENTS SCHMITT TRIGGER FOR HYSTERESIS

I designed a circuit that will employ hysteresis, so that the output of the circuit changes from logic high (+3V) to logic low (0V) or back at different thresholds depending on the direction of the change. That is, the output won't switch to logic low until the incoming signal from the V2315CF drops below 0.85V and then it won't switch back to logic high until the incoming signal rises above 4V. Any ringing in between these levels is blocked from the output. 

TESTING ONE CHANNEL WITH THE SECTOR MARKER SIGNAL

I initially only located and cut the wire that carries the signal causing me the most problems, -Sector Marker which produces a falling edge for 160 microseconds once every 5 milliseconds. This marks one eighth of a rotation of the disk platter, used by the logic circuit in the 1130 to determine where the four sectors begin on one rotation. 

A peculiarity that leads to the incorrect operation of the 1130 logic is that the disk drive reports every one-eighth of a rotation but the 1130 implements only four sectors per rotation. Therefore, it has to ignore every other sector marker pulse. The ringing in the signal from the V2315CF was causing the logic to see two sector marker pulses rather than one, so it assumed it had already moved a full one-quarter rotation. The signal conditioner should ensure it counts correctly and sees only one falling edge for every -Sector Marker pulse. 

WATCHING THE RESULT OF THE SIGNAL CONDITIONER

I put a scope on the input pin of the 1130 logic that receives the -Sector Marker pulses, to observe how the signal was shaped by my conditioner. I performed a write to a target sector, which previously had been aborting halfway through the sector due to the false edge count. The goal was to see it complete the sector write and the signal to look as close to perfect as possible on the scope.

Rising edge

Falling edge

The yellow trace at the topp is the output from the V2315CF main unit before it runs through all the cabling to get to the 1130 circuits. The purple trace is the signal received at the 1130 after the Signal Conditioner finishes with it. The blue trace is the output of the first inverter inside the 1130, showing that it also produces a single edge. 

By comparison, here are the same three signals without the Signal Conditioner aka sledgehammer - 

WILL ADD ADDITIONAL SIGNALS TO THE SLEDGEHAMMER

I picked four other signals that depend on falling edge detection in their operation in the 1130 logic, since they had the potential to trigger incorrect operation of the logic. Some won't malfunction even if they see multiple falling edges close together, such as the -Index Marker pulse that arrives once per rotation to reset the sector number counter to 0. Two edges on that signal wire still generate the same sector number in the counter. 

The incoming clock generated by the V2315CF, -Write Clock Phase B, is used by the 1130 logic to output the pulses (-Write Clock and Data) that get written on the disk platter to record both clock pulses and data bits that have a value of 1. The design of the disk produces no pulse for a data bit if its value is 0, so the only way to determine whether we have a 0 data bit value is to depend on the timing signals coming from the disk drive (or V2315CF in this case).

When reading a sector from disk, the V2315CF generates the clock and data pulses that would be extracted by the disk drive, however the data actually comes from our mini 2315 cartridges and sits in RAM on the V2315CF. Therefore, the V2315CF generates the -Read Clock and -Read Data pulses that would be seen if the disk drive heads were actually reading data from a full sized 2315 cartridge inserted in the 2310 disk drive. Those two signals are given a channel each on the conditioner board.

A feedback signal from the disk drive mechanism, -Access Ready, is used by the 1130 logic to recognize when a step of the disk arm has been accepted and when it completes. The 1130 converts a request from the program to seek a number of cylinders into a chain of small steps, a single 1 cylinder step for an odd count preceeded by 2 cylinder steps to achieve the full count. False edges might cause the 1130 to believe a step has completed when it has not, throwing off the total movement. 

I protect against false edges in the V2315CF where I watch over the arm movement, but the disk drive and the 1130 are fully in control of arm movement when we are in real mode (disk drive is operating with data coming from mini 2315 cartridge). The V2315CF has to shadow the arm movement so that it can present the data from the correct cylinder when a read or write is done - we change the RAM address based on the current arm location between cylinders 0 and 202. 

The terminator resistors for all the signals passing through the V2315CF must be pulled up to 5V in order for the 4V threshold of the signal conditioner to recognize a logic high, even though the disk drive circuits generally use 3V as logic high. This is one on the terminator board of the V2315CF. 

Another complexity of the V2315CF is my desire to support two modes - real and virtual. The intended use is real mode, where the 2310 disk drive inside the 1130 is spun up. The disk drive is passing along the real -Sector Marker and -Index Marker pulses, with the V2315CF just observing or shadowing them. The disk drive arm moves when the 1130 commands a seek to a different cylinder, with the V2315CF shadowing the end location. 

Virtual mode allows operation with the disk drive left turned off. The -Sector Marker and other signals are all produced by the V2315CF itself. It responds to the seek requests and generates -Access Ready as well. Thus, -Sector Marker, -Index Marker, and -Access Ready can come from either the V2315CF or the 2310 disk drive depending on mode.

The signals like -Sector Marker and -Access Ready are passed along through an electronic analog switch on the 2310 Interface Board which merges the wires from the disk drive, 1130 and V2315CF. In real mode, the switch connects the disk drive output to the 1130 input, while the V2315CF leaves its output line undisturbed. In virtual mode, the switch is off and the V2315CF is pulling the line down to logic low to implement those signals. 

I need the signal coming into the 1130 to work properly in both modes - real and virtual - with different electronics producing the signal in each mode. This made it impossible to select terminator resistors for an impedance that worked correctly in both modes - some choices worked for one mode but not the other. 

When these signals are conditioned by the new board, it will be time to rerun all the function tests for the V2315CF, once in real mode and another time in virtual mode. That plus the correct completion of the IBM 2310 disk diagnostic program constitute an adequate test of the V2315CF. 

Preparing wiring of the signal sledgehammer into the IBM 1130

SCHMITT TRIGGER TO CLEAN UP MESSY SIGNALS ENTERING THE 1130

I have some signals that are generated in the Virtual 2315 Cartridge Facility (V2315CF) that I built and they are fed into the disk drive controller logic in the IBM 1130. I had limited ability to change the 1130 circuitry and the connections into it. The main hardware in the V2315CF generated the signals in a FPGA and drove them out with an open collector driver and a terminator board. 

Typically the terminator board had a pullup and pulldown resistor pair to create the logic high voltage and an appropriate impedance to match to the destination. The details of the Solid Logic Technology (SLT) circuitry in the 1130 is odd by today's standards and often would not work properly when fed with the standard resistor pairs in the terminator - it might not detect a logic low reliably as one example. Thus in some cases I couldn't create a good impedance match and also get good behavior from the 1130 circuitry. I would experiment until the results were good.

When the impedance is not well matched - a difficult condition to achieve since the path from the V2315CF to the SLT input pins involved multiple mechanisms with differing individual impedances - the signal would have poor characteristics where it entered the SLT circuits. Signals may ring with substantial swings, thus swinging up and down between levels that would be a logic high and a logic low to the 1130 circuit. Sometimes the signal had an undershoot to a very negative level. 

Parts of the 1130 logic was designed around edge detection - a falling edge would trigger an action. If that action changed a counter or flipped between states, then the ringing could act like multiple edges when the intent was to have just one edge. What I needed was a way to ignore all the junk such as the ringing that occurs as part of a falling edge sent from the V2315CF, so that the 1130 sees a single clean edge. 

A Schmitt Trigger is a form of hysteresis that controls whether a signal becomes a logic low or logic high, using different thresholds for the transitions in each direction. If we don't consider a signal to be logic low until the voltage drops below 1V, but won't change it back to a logic high until the voltage rises to 4V, then all the oscillations between those voltage thresholds are ignored. 

I designed a signal conditioner that I nicknamed the signal sledgehammer because it forces a very ugly incoming signal to be a clean nice output signal. It uses an operation amplifier to force a very clean dramatic snap between logic low and logic high. Normal logic circuits can enter a grey area when the voltage is above the maximum logic low voltage but below the minimum logic high volage. This forbidden zone may produce an output that is not clearly high or low in normal circuits. Using an op amp meant that when it switched, it swung fully to the extreme. 

I used a voltage reference chip and appropriate resistors with the op amp to set it so that it would flip to logic low when the input falls down past 1V and won't flip back until the input rises up past 4V. Much more of a hysteresis spread than a typical Schmitt Trigger logic gate. I then used other circuitry to produce an SLT type output that would swing fully to its logic high (3V) or logic low (nearly 0V) following the op amp.

INTERCEPTING THE WIRING OF THE SIGNALS TO BE CONDITIONED

IBM connected the 1130 disk driver logic circuits to the internal 2310 disk drive mounted in the computer using a cable with about 20 twisted wire pairs, with SLT style connectors on each side. The SLT connector, used on the circuit cards, is a 2 column by 12 row grid of pins. The backplanes into which SLT cards plug are composed of many SLT connector slots. One of the slots in the backplane where the disk driver logic is implemented is where the cable is connected. The disk drive electronics, also built with SLT, has a smaller backplane and one of its slots is used to connect the other end of the cable. 

The V2315CF sits between the 1130 and the internal disk drive, so that it can make a mini 2315 cartridge appear to be spinning on the internal disk drive on a real 2315 disk cartridge. A 2315 cartridge has a single 14" disk platter inside the plastic enclosure. The cartridge is inserted into the 2310 disk drive and read/write heads of the disk drive will read or write data on the platter and provide it to the 1130 computer memory. 

A printed circuit board named the 2310 Interface Board has the cable from the 1130 plugged into it, rather than to the disk drive. Another cable comes from that PCB and is plugged into the disk drive. A pair of ribbon cables come from the 2310 Interface Board and connect to the main unit of the V2315CF. That unit has an FPGA, a Raspberry Pi Pico processor, RAM and a lot of interface circuitry. 

Some signals come from the disk drive and are passed directly on to the 1130. Some signals come from the 1130 and are passed on to the disk drive. The V2315CF will snoop on those signals as necessary to stay in sync with the disk drive. However, signals that would have come from or gone to the read/write heads of the disk drive are instead processed fully in the V2315CF, which creates signals that appear to come from the disk drive but are actually based on data in the mini cartridge. 

A complication is that the V2315CF can operate in one of two ways. It can completely simulate the internal disk drive, while the disk itself remains powered down. More usually, it works cooperatively with the internal drive. The disk drive spins the platter and produces timing signals (e.g. Sector Marker) that indicate where the platter is in respect to the read/write heads at any moment in time. In the other mode, the Sector Marker is generated within the V2315CF. 

Requests from the 1130 to move the read/write heads to one of the 203 tracks (cylinders) on the platter will have the disk drive move the arm with the heads. The V2315CF has to snoop on this so that it knows which track the heads are at. When the 1130 reads a sector of data, the V2315CF has to grab the data from its RAM at the location corresponding to that cylinder, so the two must stay in sync. In the other mode of operation, the disk drive does not move its arm and only the V2315CF is involved in the movement request. 

The cable from the 2310 Interface Board to the 1130 runs through the inside of the 1130, enters compartment C1 of logic gate A and is plugged into a slot of the backplane in the compartment. Its twisted wire pairs were held together with waxed string lacing then covered by a sheath of electrical tape. I can't easily intercept a signal once it enters a slot in the SLT backplane, so the cable is my point of interception.

MOST IMPORTANT CONDITIONING WAS THE SECTOR MARKER SIGNAL

My biggest challenge is when the V2315CF is in the mode where it fully simulates the disk drive. The signal -Sector Marker is produced once every 5 milliseconds during the 40 milliseconds it takes for a single rotation of the 2315 disk platter. For the 1130, IBM decided that it needed a full 10 milliseconds for a reasonable sized sector of information. Therefore the 1130 logic will ignore every other sector marker pulse. 

When doing a write of a sector of data to the V2315CF, the 1130 logic will stop the writing process when the second sector marker pulse arrives marking the end of the logic sector. The falling edge of the sector marker pulse (160 microseconds long) alternates some logic, to alternate whether the sector marker pulse is passed along or blocked. 

Because of the ugly signal arriving at the 1130 logic, the logic might see a sector marker pulse falling edge as two edges instead of one. That would mean that the write ends after only 5 ms since the blocking logic malfunctioned. 

FINDING THE CORRECT WIRE PAIR FOR THE SECTOR MARKER SIGNAL

I opened up some of the electrical tape sheathing, cut the lacing and had access to the individual twisted wire pairs near the end of the cable near where it will enter the compartment of the 1130. Using a signal tone tracer I attempted to locate the wire pair corresponding to the -Sector Marker signal. It wasn't definitive, but I also used a continuity tester hooked across the two connectors at the ends of the cable. I did locate the wire pair and cut it.

PREPARING TO SOLDER IN THE CONNECTORS TO THE SLEDGEHAMMER

I created two short twisted wire pairs that would connect to the two cut ends of the signal wire, as well as continuing the ground in the other wire of each pair. They were hooked to two connectors which will plug into the signal conditioner PCB that I had mounted on the side of logic gate A near where the cable enters the compartment. One of the short pairs goes to the input connector of the PCB, bringing the signal coming from the V2315CF. The other short pair goes to the output connector, bringing the cleaned up signal into the 1130 logic. 

Next session, I will solder these short pairs to the cut ends and insulate everything, then plug the input and output connectors to the PCB. I can then fire up the 1130 and watch the signal on an oscillocope to confirm that it looks clean. As well, I will watch the write process to verify that the full sector is written, not cut short by the defective sector marker blocking. 

Installation of signal sledgehammer into IBM 1130

FILTERING OUT RINGING AND UNDERSHOOT OF SIGNALS

The Virtual 2315 Cartridge Facility (V2315CF) sits in between the internal 2310 disk drive and the IBM 1130 computer's logic gates, either relaying signals between the two end points or generating a signal in place of the one that the disk drive might produce. I found that in virtual mode (disk drive not turned on, the V2315CF simulating it entirely), certain signals exhibit an undershoot to under -3V and quite a bit of ringing, when the nominal voltage levels are +5V and 0. 

The ringing caused the 1130 logic circuits to see the falling edge of the signal as multiple falling edges, thus confusing the logic and creating incorrect results. The path from the V2315CF to the logic gate of the 1130 is complex, with transitions between PCB traces, ribbon cables, more PCB traces, twisted wire cables, additional PCB traces, a pin on a backplane and then wiring in the logic card. There are many impedance transitions and places where signals can be distorted - made worse by a very fast falling edge because of the modern FPGA and logic gates in the V2315CF which switch so quickly. 

SIGNAL SLEDGEHAMMER IMPLEMENTS SCHMITT TRIGGER FOR HYSTERESIS

I designed a circuit that will employ hysteresis, so that the output of the circuit changes from logic high (+3V) to logic low (0V) or back at different thresholds depending on the direction of the change. That is, the output won't switch to logic low until the incoming signal from the V2315CF drops below 0.85V and then it won't switch back to logic high until the incomign signal rises above 4V. Any ringing in between these levels is blocked from the output. 

FINISHED THE BOARD WITH THE CORRECT PART I SHOULD HAVE ORDERED ORIGINALLY

Part of the design of the Schmitt Trigger uses an operational amplifier with a reference voltage of 2.5V generated by a special chip (LM285D) on my board, with the components of the operational amplifier chosen to set the low and high thresholds I mentioned above. However, when I ordered all the components to build my board, which provides five copies of the signal conditioner to handle five signals, I inadvertently ordered the LM285D chip that sets a 1.2V reference voltage, not 2.5V.

This caused the circuit to switch on at a voltage below 3V and it would not switch off even at 0V on the input pin, because the circuit was offset by the difference from my design spec. I had to order the correct part and wait for it to arrive from Digikey. I used a bench power supply to deliver 2.5V in order to validate the operation of the circuit once the correct part is installed. Once it arrived, I soldered the correct voltage reference chip on the board and went back to my testing setup. It passed with flying colors on the workbench, thus it is time to hook it into the signal path between the IBM 1130 and the V2315CF. 

CHOSE MOUNTING LOCATION AND INSTALLED THE BOARD

The main circuitry of the IBM 1130 is built into two structures (called gates) that each hold three compartments of Solid Logic Technology (SLT) cards. A backplane in each compartment hosts the slots into which the cards are plugged; some of the slots instead have a cable connector plugged in to route signals out of the comparment. The two gates are hinged at one side, so that they can be swung out of the 1130 cabinet for servicing, as well as swung apart. Normally the two sit parallel to each other and parallel to the front of the machine. 

Logic gate A is the rearmost of the two, holding compartments labeled A1, B1 and C1. Compartment C1 is closed to the hinge. The circuitry that implements the disk drive controller is installed in gate A, compartment C1. A cable runs from this location out to where the internal 2310 disk drive is mounted, normally plugged into the back of the drive. 

I built a mounting plate from acrylic and fasted that to the side of logic gate A at the hinge point. The printed circuit board with the signal sledgehammer is bolted onto that plate. Wires run from the PCB to the terminal strip in the 1130 where power is distributed, providing +12V and ground. The PCB also has two five pin connectors on it, one for inputs and the other for outputs of the five inbound signals to the 1130 that can be conditioned by this PCB.

The cable from the 1130 that is now connected to the 2310 Interface Board of the V2315CF runs from gate A compartment C1 out by the hinge, wrapped in electrical tape holding the twisted wire pairs of the signals together. I need to intercept the signals from that cable, cutting the wire and routing it through the signal sledgehammer. 

I prepared for the task by unwrapping a three inch segment of the cable to gain access to the twisted wire pairs inside. Once I identify a signal that needs to be conditioned, I will cut the white wire and expose some conductor of the black wire of the pair. The black wire is a ground signal and white carries the actual signal. I will add a short bit of twisted pair to the V2315CF side, another short bit of twisted pair to the 1130 side, and put pins on the two white wires of the new pairs. The black wires of the new pairs are joined together and joined to the exposed black wire of the original cable. 

FINDING THE WIRE PAIRS FOR THE SIGNALS TO BE CONDITIONED

I have to find which of the 20 or so wire pairs in the cable are associated with the inbound signals from the V2315CF that need to be conditioned. I purchased a signal tracer that injects a tone into a wire pair which is detected by a probe at the other end. I should be able to disconnect the cable from both the 1130 and the V2315CF, then inject a tone into the pin on the connector for each signal I need to trace. The wire can be identified, then cut so that I can insert the signal sledgehammer into the signal path. 

Once the tracer arrives, I will find the wire for the -Sector Marker signal that caused the most problem, wire it to the input and output connectors and then test the behavior after conditioning. 

Assembled and tested the Teletype ASR-33 paper tape reader power supplies

MISSING PAPER TAPE READER POWER SUPPLIES CAN IMPACT A TELETYPE RESTORATION

The paper tape reader on the left side of the model 33 ASR teletype has a power supply that feeds it 160VDC for the magnet that advances the tape. In addition, if the paper tape reader is the automatic type rather than the manual version, it has a 48V DC supply and a control relay included alongside the 160VDC circuits. 

While the power supply for the paper tape reader can be mounted up in the body of the teletype, often it was mounted down inside the pedestal stand. That freed up room for the various communications options such as a telephone dialer. It is not uncommon for someone to pick up an ASR-33 for restoration but not receive the pedestal stand. The teletype will work just fine sitting on a tabletop, except that the reader power supply will be missing, disabling the reader capability.

DESIGNED A SUBSTITUTE POWER SUPPLY FOR WHEN THE ORIGINAL ONE IS MISSING

I designed a printed circuit board based on the schematics from Teletype so that it could be connected into an ASR-33 and allow the reader to operate. The circuit is the same, although some of the components are compatible but not identical. I didn't try to match the shape and mounting exactly, since I didn't have good measurements available. 

The ASR-33 models come with a cable that has a 15 pin Molex socket on the end, meant to plug into a 15 pin Molex receptacle on the power supply card. I build my card with a 15 pin Molex connector that is hanging from the wiring coming from my card, allowing the owner of the teletype to just plug this in and have it work just like the original. 

SOLDERED TOGETHER BOTH TYPES - AUTOMATIC AND MANUAL READER VERSIONS

The manual paper tape reader version of the model 33 is operated by moving a switch on the paper tape reader to the Start position, which begins the process of reading the tape until it runs out, jams or the operator turns the switch to the Stop position. The automatic version supports a version of the switch on the tape reader that has a momentary Start position, a 'Run' position, and a momentary Stop position. In addition, if the teletype receives an XON (DC1) character, it will start reading the tape. If it receives an XOFF (DC3) character or a WHOIS (ENQ) character, it stops the paper tape reading process. 

Making a manual reader version of the power supply is done by omiting components necessary for the automatic function, such as a control relay, and wiring up fewer pins on the 15 pin Molex connector. Otherwise, the same board is used. I built two supplies for an automatic reader model and two supplies for a manual reader model, in support of someone restoring teletypes for a museum. 

BENCH TESTED THE SUPPLIES

My first test was of the section that implements the relay for the automatic reader version. This is powered by 48VAC, rectifies it with a single diode and that closes the relay. Two contacts on the relay are closed when the coil is activated, which I could check with a continuity tester. The relay began chattering, not fully closing. I finally noticed that I hadn't connected a third wire from the board to one side of the 48VAC. 

One side of the incoming AC goes through the rectifier and on to the relay coil. The other side of the relay coil is only connected to the other side of the AC input when the relay is activated. The filter capacitor across the output of the diode, however, is always connected to the other side of the incoming AC, thus there are three connections to 48VAC not two from the board. 

That caused the chattering because nothing was smoothing the 30 pulses per second of 48VDC through the coil. I added the third connection, so that one side of 48VAC went to the diode and the other side went to the other two connections; this would activate the relay with a smoother DC voltage. I tried this wiring and the relay reliably activated and released.

I picked up a 115VAC relay to act in place of the distributor trip magnet that fires off the transmission of a character that has been sensed by the paper tape reader. I also used it to act in place of the feed magnet that pulls the tape forward one position since I don't have a teletype on hand for testing. 

The process of reading begins with the circuit energizing the distributor trip magnet. The distributor in the teletype converts a 6 bit character from parallel into a serial stream with a start bit, the six data bits and the stop bits. This is done with a rotary mechanism. At the end of the rotation, the distributor activates a switch that closes the circuit to power the feed magnet in the tape reader. This causes the tape to advance one position, after which the distributor trip magnet is again energized unless we are stopping the reader. 

I used the inexpensive relay I bought to observe the operation of the circuitry, verifying that closing a switch (simulating the end of a rotation of the distributor) will energize the relay that is simulating the feed magnet. This section is driven by the circuit that rectifies the 115VAC into 115VDC to activate the feed magnet. 

Testing the 115VDC circuit, I saw the current limiting resistor emit a burst of light as a thin slice vaporized. This is a 22 ohm resistor in the input line to the bridge rectifier, whose peak load is when the AC mains are first turned on and the filter capacitor of the bridge rectifier is charging up. The surge is very brief but will definitely blow out a normal resistor type which is what I used. Wirewound resistors are typically used as they can absorb the very brief surge without failure. 

I will install 5W wirewound resistors on the boards instead of the surface mount part I originally used. There is a good surface mount part that I could have put on there, but it would require a new version of the PCB since it is larger than the footprint of the original part I used. The original was a 16W component with a very large SMD size already, but less than the wirewound SMD part requires.   

For the automatic version of the power supply I operated some switches that stand in for the momentary Start, the momentary Stop, as well as the XON, XOFF and WHOIS detection switches. I checked that the relay on the power supply board activates and turns off appropriately based on those simulated switches. I also verified that the distributor trip magnet (the relay simulating it) activates when the control relay is turned on and does not activate when it is turned off. 

Once the functions were validated and the voltages and currents verified, and the new resistors installed, it will be time to pack these up and ship them off to the restorer who is waiting for them to make use of the paper tape reader. 

Built my signal sledgehammer for the Virtual 2315 Cartridge Facility and gave it a test

SIGNAL ISSUES TO BE ADDRESSED BY THE CONDITIONER

Certain signals produced by the Virtual 2315 Cartridge Facility (V2315CF) that drive logic in the IBM 1130 have significant ringing, bounce and undershoot problems due to the nature of the wiring that ordinarily connects those 1130 circuits directly to the internal 2310 disk drive in the computer. The V2315CF sits in between the two and generates some signals in lieu of the disk drive. 

Logic in the IBM 1130 is often designed around edge detectors, so that a ringing signal can pr,esent itself as more than one edge which causes the 1130 disk controller logic to malfunction. I have particularly observed this when the V2315CF is operating in virtual mode; the -Sector Marker signal exhibits the signal quality issues because it is generated by the FPGA and fast gates in the V2315CF, unlike real mode where the 2310 disk drive creates those signals. 

DESIGN OF THE CONDITIONER

The conditioner is designed to employ hysteresis, holding the state of the output steady during the perturbations of the bad input signals. It will not respond to an input level above 0.85V when the input was logic high and begins dropping. Once it hits that low threshold, the output switches to logic low state and won't exit that condition until the input signal climbs to at least 4V. All the undershoot and ringing that happens with the input signal is masked, giving a single clear falling edge to logic low. 

I used an operational amplifier circuit as the Schmitt Trigger, with the components chosen to cause it to switch to logic low when the input goes below 0.85V and to switch to logic high only when the input goes above 4V. The op amp is then buffered by a MOSFET and the output of the MOSFET is inverted by a bipolar transistor to create an output signal at the appropriate voltages for the 1130 circuits receiving the signal.

I created a board with five channels - five identical signal conditioning circuits as described above - plus an onboard voltage regulator and a reference source at 2.5V for the Schmitt Trigger. This is intended to be mounted on the end of logic gate A in the 1130, close to where the signal cable enters compartment C1 housing the disk controller logic. I will cut the wires of the signals that need conditioning, pass them through a channel on the board and then into the 1130. 

SOLDERED TOGETHER THE BOARD AND COMPONENTS TODAY

I had received the parts from Digikey and the printed circuit boards from JLCPCB thus I did the assembly today. After soldering all the parts onto the board, it was ready for testing. First I would test its functioning on the bench and then install it to condition the -Sector Marker signal and observe the behavior of the 1130 logic. 

TESTED THE CONDITIONER - DISCOVERED I ORDERED THE WRONG PART

I set up a bench test to verify the hysteresis behavior, varying the input voltage and observing the output line. I saw it switch too early, well under 4V, and then refuse to switch back to off even when the input voltage was zero. 

I checked the voltages on the board and discovered that my voltage reference, which should establish a 2.5V level for the op amp schmitt trigger behavior, was sitting at 1.2V. A careful read of the package made clear that this was in fact a 1.2V reference part, and that was what I had ordered somehow. 

I put in an order for the correct part but this means I have to wait about four work days before I can finish the validation test and then put the conditioner into the circuit between the IBM 1130 and the V2315CF. 

USED TIME IN THE SHOP TO FINISH THE CONNECTORS FOR MY ASR-33 POWER SUPPLIES

I wired up two connectors for the automatic reader version of the Teletype model 33 paper tape reader and two connectors for the manual reader version of the model 33. These are ready to solder onto the boards when I build them tomorrow. Digikey delivered my parts today and the DHL truck is wandering around in my area with the PCB shipment.

FURTHER GLUE WORK ON THE V2315CF CABINET

I added braces and set up the holes for screws to allow the top panel to be removed for servicing. I have to drill the matching holes in the top plate and drill several mounting holes in the bottom plate to complete the construction so that the cabinet is ready to attach to the 1130 system permanently.

Parts arriving and work begins on both Schmitt Trigger Conditioner and the ASR-33 Reader Power Supply

PCBS AND ALL COMPONENTS CAME TODAY FOR THE CONDITIONER

The boards arrived from JLCPCB today, the components that came earlier this week from Digikey. Tomorrow I can solder together a board, giving me five channels of incoming signals from the Virtual 2315 Cartridge Facility (V2315CF) that I can condition so that they deliver reliable edges and no bounce or glitches. 

The signals are generated by an open collector gate in the V2315CF that is driven by the Lattice FPGA. It produces such sharp edges when it pulls the signal low that at the other end, where the signal enters the IBM 1130's Solid Logic Technology (SLT) circuitry, we get undershoot and ringing which can appear to the SLT logic as more than one falling edge. This throws off the logic and produces erroneous results. 

The conditioner employs hysteresis, via a Schmitt Trigger operational amplifier (op-amp) whose thresholds are 4V and 0.7V. This ensures that once a signal drops below 0.7V, the SLT logic sees a logic low and  will not see any change until the input passes above 4V where the SLT input becomes a logic high. All the ringing below the 4V level is completely ignored. The undershoot is ignored as well. 

MOLEX CONNECTOR PARTS ARRIVED AND FIRST CONNECTOR WIRED UP

The shipment from Mouser arrived with the Molex 15 pin connector bodies and male pins needed to create the plug that the Teletype Model 33 ASR connects to for the purpose of powering the paper tape reader and implementing the automatic start and stop of the reader. I assigned wire colors to the 13 connections on the plug that are implemented. Two pins are used on the original Teletype power supply to complete a circuit when the reader is running - that circuit is available for custom purposes and not used in the machines where my replacement power supply will be used. 

EXPECTING PARTS TOMORROW AND PCB ON MONDAY FOR READER SUPPLY

The other components for the power supply are arriving tomorrow from Digikey and the PCB for the supply is expected to be delivered Monday, after it was produced at JLCPCB. Thus on Monday I can solder together four of the PCBs, creating two power supplies for the automatic reader version of the ASR-33 and two supplies for the manual reader version. The manual reader version simply omits some components on the PCB and the associated wires to the Molex connector. 

GLUE UP OF CABINET FOR VIRTUAL 2315 CARTRIDGE FACILITY BEGUN

I began gluing together the acrylic pieces that form the cabinet for the V2315CF. This consists of multiple sheets of acrylic, laser cut to dimension, with rectangular rods used as braces at all the intersections. I leveraged a wood box for its right angles and good support, adding clamps to hold the parts together while the acrylic glue joins the pieces. 

Quick side project - power supply for ASR-33 Teletype automatic tape reader

LEARNED THAT SOMEONE RESTORING ASR-33'S LACKED THE POWER SUPPLY

The Teletype ASR-33 comes with a paper tape reader attached to the left side of the body. There are two flavors of the tape reader - manual and automatic. The manual one is started by the operator flipping a lever to start and stopped the same way unless it runs out of tape first. The automatic one can also be started by characters sent over the serial line from a remote system. The XON character, called DC1 by Teletype, starts the tape reader and receipt of an XOFF, called DC3, stops the process. The ENQ character (named WHOIS by Teletype) will also stop the tape reader since it triggers the machine to transmit a sequence that is hard coded into a drum inside the body. 

The power supply for the manual version of the tape reader has to power the feed magnet, a coil in the reader that drives the tape forward one sprocket hole each time it is energized and released. The power supply rectifies the 115VAC building power and creates 150+VDC to activate the feed magnet. A switch inside the body of the teletype is triggered each time the distributor is released and makes one revolution. The distributor converts parallel data, from the keyboard or the reader, into a serial bit stream for transmission. 

The start switch on the manual reader activates another magnet which triggers the distributor to turn, serializing and outputing the character that the reader just sensed. When the switch is turned to stop, or errors such as end of tape or tape too tight occur, the magnet stops activating the distributor and once it finishes its last rotation, the feed magnet stops advancing the paper tape. 

The automatic reader implements a relay driven by rectifying the 48VAC supply inside the teletype. The reader power supply takes in the 48VAC from the other power supply, makes it DC and limits the current. Contacts on the relay form part of the logic that controls when the reader will run or stop.

The relay can be activated by the switch on the reader, much like the manual reader operation, but can also be activated by the XON character being decoded by the printing part of the teletype because it received that character from the remote system. The relay keeps itself latched until one of a few things break the circuit to deactivate it. The switch on the reader can be moved to stop. The XOFF or ENQ character can be received by the printer. Various errors such as tape too tight or tape running out can also stop the reader. 

ASR-33 Teletypes come in many configurations in addition to the chose of automatic or manual reader. They can have phone dials, interfaces to advanced communications systems, or just hook up to a current loop serial interface. Depending on those other options, the power supply for the paper tape reader can be installed in the space that holds those other functions, or it can be placed down inside the stand on which the body of the Teletype sits. 

The units that are being restored came without the stands. They will work just fine sitting on a tabletop, but the automatic reader one lacks the reader power supply that was in the missing stand. The restorer was happy to look for additional teletypes or parts that might have the reader power supply up in the body, but that was currently holding up completion of the restoration. 

I DESIGNED A REPLACEMENT POWER SUPPLY FOR THE AUTOMATIC READER ASR-33

The schematics from Teletype show the power supply board and all the components, with their values. It was easy to whip up the schematic in KiCAD and then design a PCB to implement the same circuit. I located all the components needed and put them in a cart on Digikey.com, then looked at the cost to fabricate the PCB using JLCPCB. 

The PCB order comes with five boards and that means I could build up to five power supplies. The manual reader version leaves out a number of components, including the relay, but can otherwise be built using the exact same PCB I had manufactured. The per board cost for components run from $22 for a manual reader to $31 for an automatic reader type, with the shipping from Digikey amortized over the number of boards I build. 

I am waiting to order components while the restorer assesses how many of each he might need. Within a couple of weeks I will be able to complete these and get his restoration back on track. 

Automatic Reader power supply board

Bringing out the signal sledgehammer - dealing with the signal quality issues for the Virtual 2315 Cartridge Facility

GLITCHES CAUSING PROBLEMS IN SOME FUNCTIONS

Virtual 2315 Cartridge Facility (V2315CF) attaches to an IBM 1130 computer system, working with the internal 2310 disk drive, to allow mini versions of the disk cartridges (2315) to be used rather than having the data stored on the 14" platters in a 2315 cartridge. Part of the function of the V2315CF is to generate signals that are delivered to the IBM 1130 disk controller logic, substituting for signals that are generated by the 2310 disk drive in an unenhanced 1130 system.

The electrical path from the V2315CF to the 1130 logic is complex and results in ugly signals at the input pins of the logic gates in the 1130. There is quite a bit of capacitance, multiple segments with differing impedances, and very fast signals produced by the Lattice FPGA in the V2315CF whose sharp edges create issues that don't exist for signals created by IBM's Solid Logic Technology (SLT) which is much slower and non-standard compared to modern digital technology. 

There are many places in the 1130 disk controller logic where glitches or ringing don't cause a problem, because the state of the signal is employed over a relatively long timeframe. However, there are circuits that respond to the edge of a signal and advance counters; these circuits can see a glitchy signal as multiple valid edges, leading to defects in the operation of the input-output operation to the disk drive. 

The traces above are the falling edge of the -Sector Marker signal that is generated by the V2315CF when it is fully simulating the 2310 disk drive. In a different mode (real), the V2315CF passes the signal from the 2310 disk drive to the 1130 but in this mode (virtual) the V2315CF has to create the signals. The yellow signal is the output of the main V2315CF box where it generates the falling edge of the signal. Purple shows the signal as it arrives at the input pins of the 1130 logic, at logic gate A, compartment C1. The blue signal at the bottom is what the purple input looks like after it has passed through an inverter gate inside the 1130. 

The signal exhibits a major undershoot as well as ringing. The SLT nominal voltage levels are +3V for logic high and 0V for logic low, but the reality of SLT gates is different than one would expect. It does not care about the undershoot, something that would devastate a TTL or CMOS logic device of modern times. 

Further, the actual mechanism of operation of the input is having current sink from the SLT input to the driver, somethat that occurs when the voltage at the input is at 0.7V or lower which causes a current to flow through a diode of the SLT input because of the voltage differential, sufficient to switch off a transistor in the SLT gate to produce the inverted output. Only that current flow causes the SLT gate to see the input as logic low. It must be a large enough current, e.g. 1.5 or 2ma, to activate the SLT gate. 

Equivalent of SLT inverter gate

If there is an open circuit to the input pin, the SLT gate treats it like a logic high. If the voltage is 2V or 10V, the SLT gate treats it like a valid logic high. There are input voltages that may be in a forbidden, zone, not clearly switching the SLT transistor on or off - 1.2V is not enough of a differential to achieve the 1.5ma necessary to completely shut off the transistor and let the output pull up to the 3V logic high level. 

In the purple trace above, the signal at the V2315CF has a pullup resistor to +5V and an open collector gate that turns on to create that falling edge. The signal only pulls up to 4V on the scope because of an effective voltage divider which absorbs 1V. By the time we see the signal at the far end of the cabling, at the 1130 input pin, it is fully at 5V when in logic high state, but drops way below 0V because of the impedance of the pathway, including capacitance as well as resistance. The signal drops down to -4V at the bottom of the undershoot before returning to the zero volt level where we see it ringing or oscillating at that level. 

The swings above zero during the ringing bring the SLT gate input into the forbidden zone, not fully cutting off the SLT gate transistor. We see the output of that SLT gate in the blue trace climbing up to the 3V nominal logic high voltage, but doing so in a see-saw climb because the transistor in the gate is not fully cut off. I believe this particular trace did NOT cause the 1130 to see two different edges, errors that occur sporadically and not on every activation of -Sector Marker from the V2315CF. 

IMPEDANCE IS VERY CHALLENGING

Unlike connections that run over a single cable with a uniform construction, the signals coming from the V2315CF have a complicated routing where each segment can have its own impedance. The signals run over PCB traces to a ribbon cable, very similar to those used with IDE disk drives in more modern computers. This section is going to have an impedance somewhere just over 100 ohms. The signal is connected to my 2310 Interface Board where it is routed to a pin on a 12x2 pin connector. That is, it is routed that way when we are in the virtual mode we are debugging here. 

12 twisted wire pairs form a long cable bringing the signals from this board to the logic gate A of the 1130. In an unenhanced 1130 system, this cable plugs directly into the 2310 disk drive. These are single ended signals on the wire bundle, perhaps 4-5 feet long. IBM tends to design these cables for a characteristic impedance of around 92 ohms when using their flat ribbon cable connections. These loosely twisted wire cables have an unknown impedance. With the V2315CF, the wire bundle from the 1130 logic gate plugs into my 2310 Interface Board. Another cable that I produced runs from a second 12x2 connector and plugs into the 2310 disk drive. My board allows the V2315CF to sit in between the disk drive and the 1130, controlling some signals while passing others through unmodified. 

If we run in real mode, an analog switch chip connects the pin for out signal on the 12x2 pin connector for the 1130 logic wire bundle, routing it to the 24 wires coming in from the disk drive to the second 12x2 connector, so that the disk drive electronics are directly producing the -Sector Marker pulses. Our open collector gate is left at logic high, so it has no effect on the signal. This pass through does see the pullup resistor on the terminator board in the V2315CF, part of the reason that we don't see the full 5V at that point. 

However, the circuit card in the disk drive that produces the signal is not one for which I have the schematics. I don't know the circuit structure nor the resistors used for pullup on that driver gate. All I know is that when the disk drive is connected directly to the 1130, those pulses are correctly handled by the 1130 logic without undershoot or ringing. 

In virtual mode, the terminator board at the V2315CF attempted to manage impedance matching for the signal going from V2315CF to 1130. Some I had tuned to 110 ohms for correct operation, some only worked with much higher value pullup and pulldown resistors so that there was a big impedance mismatch but the voltage swings were correct as seen by the 1130 logic.

The most direct method to handle issues like this is to change termination at the 1130 end, but that is mechanically difficult. The cable connector of the wire bundle from the V2315CF plugs into one slot of the backplane of compartment C1 of logic gate A. The backplane has an array of 7 rows by 11 columns into which SLT cards are plugged. Each slot is 12 rows by 2 columns of pins. The rows are numbered 2 to 7 and the columns are labeled B through M. In addition, slots in the leftmost and rightmost columns (A and N) are used for cables that run between backplanes (compartments) or to other devices. As well, slots for connectors are implemented in rows 1 and 8 for top and bottom cable connections. 

The wire bundle for the disk drive is plugged into column N, row 7 (slot N7). The signals are routed as PCB traces over the backplane to various slots where the connect to a pin of an SLT card when it is plugged in there. For the -Sector Marker signal, it is connected to pin D12 (left column and next to bottom row when viewed from the wirewrap side) of slot L4 which is the input to the SLT inverter on the card plugged in there. In many cases, a signal goes to multiple pins at different slots, but this one signal is the simple case. The signal than flows through the connector and onto the SLT card plugged into L4, where is makes its way to the diode for the input. 

Each discontinuity - wire bundle to connector pins to backplane traces to SLT card slot pin to card trace - plus any wirewrap connections that augment the connections on the backplane - are spots where the signal can reflect, the impedance can change, and of course all that metal generates a significant capacitance. There is no clean way to calculate the effective impedance; all I can do is observe signals and adjust things where I can to reduce artifacts and issues. 

CHALLENGES ADDING TERMINATION OR OTHER SIGNAL CONDITIONING AT GATE A

Unless I cut the wire bundles or cut traces on the backplane, I can't intercept the signal coming in. I have access to the pins of the backplane but they are pretty close together and many have wirewrap connections added. The backplane has 6, 370 holes spaced .125" apart, many with pins that form the slots for SLT card and cable connections. Adding discrete resistors for termination takes up too much space and blocks access for probing signals during debugging. Because of the wirewrap, a teeny PCB to slide over pins would sit at an uneven height. It would also restrict the ability to push probes for logic analyzers or scopes onto pins that go through that PCB.

FINALLY PULLED OUT THE SLEDGEHAMMER TO STOMP OUT THE SIGNAL ISSUES

All the issues above are why I was loathe to try to resolve the signals where the entered into logic gate A. However, the dual modes of the -Sector Marker where it either comes from the V2315CF or the 2310 disk drive, made if very hard for me to produce a termination scheme at the V2315CF which works properly in both modes. 

Therefore, it is time to add some circuitry of my own that will take the signal as it arrives to the connector N7 of the backplane, intercept those that are susceptible to errors due to the signal quality, and transform the signal into something that cannot be seen as multiple edges or push SLT gates into the forbidden zone where their output is not well behaved.

I am going to depend on hysteresis to resolve the problems. I know that when the signal transition starts, the voltage is up at about 5V and when it finally stabilizes it is at 0V, but with all the undershoot and ringing occuring. If I can introduce rules for detecting the transition that block all the effects of the signal issues, I can then generate a SLT style signal into the SLT logic gate that is clean and well behaved. 

The Schmitt Trigger is a device that applies hysteresis to signals. A Schmitt trigger changes from logic high to logic low when the voltage coming it drops to trigger voltage A, but won't switch back to logic high until the voltage climbs up to trigger voltage B. Modern ICs can have Schmitt Trigger inputs to remove short bounces in the signal state as a signal transitions from one state to another, but these devices don't have a wide enough span between trigger voltages A and B to clean up the signals I am seeing. Further, modern chips won't do well with a large negative undershoot.

I therefore created a design that uses an operational amplifier (op amp) as a Schmitt trigger so that I could select the trigger voltages. I choose 1V as trigger voltage A and 4V as trigger voltage B. The op amp will swing hard over from one output state to another as the input voltage crosses these trigger levels. When the input voltage first drops down to 1V or lower, the op amp will swing hard over to the low state and will not react until the input voltage climbs up to at least 4V. It also doesn't care if the input voltage goes negative. Once an input climbs up to 4V, the op amp swings hard over to the logic high state and won't leave that until the input gets below 1V.

I then had to deal with the reality that SLT gates are activated by a 1.5 to 2ma current being pulled out of the input pin, not by a voltage level. To deal with that I put an NMOS MOSFET transistor on the output of the op amp. The rail voltages of the op amp are big enough that when it is in the logic high state, the MOSFET is fully switched on and when it is in logic low state, the MOSFET is fully off. The op amp slams almost instantly to one state or the other based on the trigger levels and the input signal. 

When the MOSFET conducts, it pulls the base junction of an NPN transistor down to effectively 0V, cutting off the transistor. A pullup resistor on the NPN transistor makes the output of my sledgehammer high when the transistor is cut off, but for SLT that really isn't a factor, It is helpful for debugging to see a logic high voltage on a scope or logic analyzer, but only effect that matters to the SLT inverter gate is when the transistor is conducting, because it sinks enough current from the SLT gate input to trigger it on. 

One of five channels

Dealing with the signal realities coming into logic gate A compartment C1 and the electrical realities of IBM SLT gates thus involves an op amp to implement the two widely spaced voltage thresholds, a MOSFET to react to the voltage levels of the op amp without loading it down, an NPN transistor to sink 2ma from the SLT gate, and a 2.5V voltage reference that is a key part of the op amp circuit. Three chips and five resistors, plus the voltage reference and a clean power supply for the components, all simulated on LTSpice and behaving just as I want. 

5V supply from 1130 +12VDC

2.5V reference generator

Due to realities of the MOSFET and NPN, the final voltage thresholds work out to be 4V going up for the signal to be logic high and 0.85V going down for the signal to switch to logic low. Based on the signals coming in from the V2315CF, those thresholds work out perfectly to hammer the ugly input signal into a clean and and off signal local to the logic gate that I can route to the SLT card input. 

To intercept the signal, I have to cut the wire bundle near where it enters the logic gate so that I can route it through my sledgehammer fix. It is cumbersome to do this at that point because the logic gate swings on a hinge right where the wire bundle is passed through a railing into the compartment. I will have to figure out a way to mount my new PCB with the circuits as close to where the bundle enters compartment C1 as I can get it to minimize any load on the signal going from my board to the SLT card input pin. 

I chose to design a card with five channels of sledgehammer on it. I know that the -Sector Marker signal is a problem and I had just barely gotten the -Write Clock Phase B signal to behave by juggling terminator resistor values at the V2315CF, so those two are certainly going to need help. I can imagine two or three others that might benefit from the cleanup. 

The way that the 1130 deals with data is is reading from disk, e.g. data that the V2315CF is generating from the contents of the mini 2315 cartridge, makes it insensitive to glitches and double edges because there is a strict alternation of pulses from the -Read Clock signal and either a pulse or no pulse on the -Read Data signal line. All the logic cares about is whether it saw an pulse at all during the time when a data bit will arrive - two or more edges are still seen as the presence of a pulse. 

The value of the -Read Clock signal is used to shift in a bit and later listen for a data pulse, so the clock signal might need the assist. That would bring the total to three, so I have a few spare channels for anything else I discover in the future. 

ORDERED COMPONENTS AND SENT THE PCB OUT TO JLCPCB FOR FABRICATION

I should have a finished PCB to test with in a couple of weeks or less. I will look around to see if I can breadboard up a circuit in the lab for some early testing of the effect it has on the signal. I think I have suitable op amp and NMOS devices on hand. 

Results of latest logic analyzer capture of write on Virtual 2315 Cartridge Facility

CAPTURE SET UP TO UNDERSTAND WHY WE ARE BUMPING ADDRESSES WEIRDLY

The observed symptom was that when I did an XIO Write command with a buffer filled with 321 words whose values were essentially the same as their word number, thus easily identifiable, the Virtual 2315 Cartridge Facility received the first 111 words of the buffer correctly but then had a strange pattern seemed to be captured for the rest of the sector. We jumped up to word 225 and then were sent every OTHER word in the buffer from that point, meaning the memory address the 1130 was using to fetch memory from the buffer was advancing by 2 instead of by 1.

The logic analyzer produced a spreadsheet that I analyzed with a quick Python program to find the clock transitions and capture the data bit values, assembling them into 1130 words and validating the error checking code bits. Below is the beginning of the capture, which matches the pattern I wrote into the memory buffer for the XIO Write instruction. It shows the relative timing in microseconds from the start of the write operation as well as the extracted word. It would flag any error checking violation to the right of the word. 

Below is the area in the data capture where we see the jump in core memory addresses and the stride of memory addresses increasing to 2. We should be fetching 0x0071 next but instead grab 0x00E2 and then step by twos through the remaining words. 

I realized after a long while that in fact the value I believed to be 0x00E2 was actually 0x0071, the bits apparently shifted left, with the ECC check passing because the word had four bits that were 1, so the ECC value would be 0000. I looked closely at the graphical logic analyzer trace and confirmed that I was seeing the data fetched correctly from memory but shifted a tad due to a glitch on the -Write Clock Phase B line. 

The hardware that requests the memory fetching is designed with only one function - increment by 1 - which occurs at the end of the memory fetch of a word so that the address is bumped to the next position. In modern logic, this is a ripple counter.

I don't see any mechanism that would explain the big leap somewhere in the middle of correct operation nor the double stride used for the rest of the write. I put the logic analyzer on all the address bits coming from this ripple counter and saw it perform perfectly. 

RESULTS OF THE DATA CAPTURE INSTEAD POINTED AT GLITCHES IN SECTOR MARK

What I saw in the traces, particularly the fact that the trailing words of the sector were all zero values, were the expected behavior if a write operation stops too early. The design of the 1130 keeps sending zero words until the actual end of the sector even if the word count for the write command has reached zero earlier. Assuming that bad addresses were fetching words from 1130 memory that all were coincidentally zero was a leap of faith, and unwarranted. 

Looking at traces I captured, I found that -Write Gate was turned off at the 5 millisecond point instead of remaining on for the entire 10 ms duration of a sector. This turned my suspicion back to the physical sector mark pulse that was arriving around the point we stopped grabbing data from the 1130. 

The drive produces eight 160 microsecond pulses spaced evenly around the perimeter of the disk platter, one each 5 ms given the 40 milliseconds it takes for the disk to spin once at its 1500 RPM nominal speed. IBM chose to divide the perimeter into four sectors rather than the eight defined by the hardware pulses. This allowed enough space on the logical sector to write 321 data words. 

To accomplish this, the 1130 disk controller logic implements a simple divide by two circuit using a flipflop that is toggled by the physical -Sector Marker pulse coming from the disk. IBM's Solid Logic Technology (SLT) circuitry in the 1130 uses flipflops that are triggered by a falling edge of a signal. 

They also produce a parasitic false output pulse if the set or reset input is pulsed when the flipflop is already in the requested state. IBM designs around this by adding gates in front of the set and the reset inputs that only allow a pulse if the flipflop is not already in that condition. 

The gates in front of the flipflop are also edge triggered - IBM calls these AC triggered gates. When the trigger signal, marked with the letter N on the input of the gate symbol, has a falling edge, the gate produces a short negative going pulse on the output pin on the right of the gate symbol. However, it is only sensitive to the input falling edge if the other inputs, marked with a right triangle symbol, are at logic low (0V). If any other input is high, the gate ignores the falling edge on its trigger input and does nothing.

Thus, in the logic diagram excerpt below, when the trigger input goes low, the non-inverted output of the flipflop is connected to the gate in front of the flipflop set input. When the flipflop is on, the non-inverted output is high and that prevents the gate from sending a set pulse to the fliplop. When the flipflop is off, the non-inverted output is low and the gate can send a pulse to set the flipflop on.

However, the gate connected to the reset input of the flipflop is conditioned by the inverted output of the flipflop. If the flipflop is already set, the inverted output is low and that allows the gate to send a pulse to reset the flipfop. When the flipflop is not set, the inverted output is high and the gate blocks a reset pulse from being applied. 

The -Sector Marker pulse from the disk drive sits at logic high except for 160 microseconds, once every 5 milliseconds while the disk is rotating. The inverter gate at the top left changes the signal so that it is low most of the time and goes high for 160 microseconds. When the 160 microseconds ends, the falling edge of that signal is passed to the two gates that drive the flipflop set and reset inputs. The action of the two gates means that it toggles the flipflop to its opposite state by routing a pulse to either the set or reset input depending on the current state of the flipflop.

Thus the flipflop goes on and off based on the end of the -Sector Marker pulse. The gate at the top right of the diagram is a simple combinatorial NAND gate. When the inverted -Sector Marker pulse, now high during the 160 uS interval, occurs while the flipflop was set, the 160 uS signal passes through as a negative going 160 uS pulse once every other sector marker. In essence, the top right gate blocks every other sector marker pulse. 

In addition to the eight sector marker pulses that arrive as the disk platter rotates, there is one -Index Marker pulse of 160 uS per rotation that marks which sector is number 0 out of the four logical sectors that pass by the read/write heads during a spin. At the bottom, the -Index Marker pulse negative edge, when it begins its 160 microsecond duration, will force the flipflop to reset so that we are set up to block the next sector marker. 

The index marker occurs just after one of the eight sector marker pulses, so that this position on the disk marks the start of a logical sector, blocking the next sector marker and passing the one 10 milliseconds later. This keeps the disk controller in sync with which sector is arriving next for when a read or write operation must start. 

Astute readers might wonder at the risk of the parasitic output pulse since the index marker pulse might reset a flipflop that is already in the reset state. Indeed that blip might be emitted on the non-inverted output of the flipflop if it was already reset when the index marker arrives. That does cause the top right gate to have a short term high on one of its inputs, but this does align with when the sector marker pulse is active so nothing comes out of the final gate. The timing diagram below shows how this works out:

With this background, you can see how my next logic analyzer trace captured the cause of the short write duration. We were watching the signals involved in switching off a write operation, The important signals to look at are the -Write Gate, -Four Sector Pulses, +Sector Marker (the inverted output of -Eight Sector Pulse from the logic diagram above), +Alternate sector (non-inverting output of the flipflop), and -Alternate Sector (inverting output of the flipflop). 

On the left of the trace, we have the first sector marker, the one that defines the start of the sector we are writing to. The inverted sector marker pulse goes high for 160 uS. The falling edge of -Sector Marker, rising on the inverted signal, turns on -Write Gate to begin the sector. The flipflop resets at the trailing edge of the inverted signal +Sector Marker which would block the next sector marker pulse from passing through to the output of the logic diagram as signal -Four Sector Pulse. 

However, when that next sector marker pulse arrives, we get a glitch that appears as a short sector marker immediately followed by the normal sector marker. The falling edge of +sector marker causes the flipflop to be toggled, then the remainder of +Sector marker passes through as -Four sector pulse and turns off our write. We end prematurely because of the glitch - had the pulse not had the brief blip down, we would have blocked the -Sector Marker and not reacted.

The flipflop is reset at the start of the true sector, but sets briefly before resetting again when the second -Sector Marker ends. The signal line where I produce the -Sector Marker pulse is kind of unique, as it is generated by the V2315CF when in virtual mode, but we pass along the real disk drive pulses when we are running the real (hybrid) mode. 

COMPLICATIONS OF REAL AND VIRTUAL MODE

Some signals between the disk drive and the 1130 disk controller logic are always coming from the V2315CF, such as the -Write Clock Phase B, while others may come from the disk drive OR the V2315CF depending on our mode of operation. The normal mode for the V2315CF is called real, where we spin up the internal 2310 disk drive inside the 1130 and let is generate signals such as sector mark, index mark, file ready, access ready (for seek operations moving the disk arm) and home cylinder. The V2315CF watches those signals and keeps track of what the real disk drive is doing. In virtual mode, we leave the 2310 switched off and simulate all the signals from inside the V2315CF.

Electrically, we bridge the signals from the disk drive to the 1130 controller logic using electronic analog switches on the 2310 Interface Board, a component of the V2315CF. When the switch is set to real mode, the analog switches are closed and they route the signal coming in from the 2310 to the wires going out to the 1130 disk controller. The FPGA logic in the V2315CF does not emit anything on those signal lines while in real mode; since the outputs are open collector gates, we emit a logic 1 to leave the output line undisturbed. The 2310 disk drive provides a pullup resistor to logic high (3V for SLT) and grounds the signal line to send a logic 0. 

In virtual mode, the switches are disconnected and the signal is produced by sending logic 1 and 0 values to the open collector output gate. To provide a pullup because the 2310 is no longer operating,  we depend on two things. The termination resistors on the V2315CF have both a pullup to +5V and a pulldown to ground, with the resistor values creating an impedance match to the ribbon cable and other wiring. They are set to give a logic high value of 3V at the signal line when our open collector driver is at logic 1 and pull down to ground when the driver is emittiing logic 0. 

The challenge is how to handle pullup resistors and termination resistors for when we are in real mode, where these can interfere with the pullup resistors in the 2310 disk drive circuit. I changed these to a much higher set of values that will still set 3V when in virtual mode but have light impact on the levels produced by the 2310 circuit when we are in real mode. 

Because the electronic switch is shorting the 2310 signal to the 1130 disk controller input, our terminators are mid stream and don't do much for real mode, but work adequately when in virtual mode. They have the downside that they don't match the impedance well in virtual mode, acting as a 6K ohm termination for a 100+ ohm line. 

This can give us ringing and glitches, something plaguing the sector marker signal right now. When I had the sector marker terminator resistors at the correct impedance matching - 169 and 249 ohm values - the glitches showed up in the operation. That matched the traces I just showed.

When I pulled the terminator resistors off entirely, the write failed in a different way due to glitches.

Here the glitch occurs on the sector marker pulse at the start of the logical sector. There is a glitch on the falling edge of -Sector Marker (inverted -8 sector pulse is a rising edge in the trace). This toggles the flipflop twice, thus it is set up to incorrectly pass the next -Sector Marker pulse through and stop the write prematurely. 

The issue with the first trace was a glitch during a rising edge of the generated -Sector Marker from the V2315CF in virtual mode, while the second trace shows a glitch on the falling edge. The input gate that accepts the -Sector Marker signal and inverts it for the logic diagram excerpt above has the following actual circuit values (using germanium diodes and transistors with .3V drops):

SLT logic is a form of Diode-Transistor Logic (DTL), which actually switches based on the current that sinks through the input pulling down the junction of the two diodes to cut off the conduction of the transistor. The current creates a voltage drop across the 2K resistor. 

In the absence of any connection to the input pin, the transistor base is seeing a voltage well above its .3V activation level, The transistor conducts to pull the output pin down to essentially 0V. With a current flowing out of the input, the voltage drops at the junction and when it gets down to about 3.3V the transistor will be cut off entirely, letting the output pull up to nearly 3V. A 3V drop on the 2K resistor comes from an input current of 1.5 milliampere. 

The nominal logic high value for the input is +3V, which means that the gate could deliver current into the input from the 2K resistor based on the voltage difference between the input pin voltage and the +6V pullup. It is possible to drive current into the power supply of the gate up through the pullup resistor. With the V2315CF, that is the terminator resistor pair dividing up the current sink between the pullup to 5V and the pulldown to ground. Since that looks like about 100 ohms, the current would be around 1.28ma. 

With SLT, it is simply the pullup resistor which is often 750 ohms, reducing the current being sunk to less than 1 ma. Interestingly, the input does not have to provide a voltage at all in order for the SLT gate to see this as a logic 1 input. Unless then input pulls at least 1.5ma of current down through the input, it appears to be logic high. An open pin is the same as a logic 1 pin, other than the lack of any current backflow into the input. 

While I know the exact circuit values for the components in that inverter gate above, other circuits that take signals from the V2315CF, such as -Write Clock Phase B and -Sector Marker used in different places go to SLT cards for which I do NOT have schematics. I can model the behavior of the connection from the V2315CF to the inverter for generating the -Four sector pulse output, working out termination resistor values that give proper results, I can't do that with the other gates accepting signals from the V2315CF. 

Some signals are used in ways that make glitches or ringing a non-issue. -Index Marker is one where we don't care if we reset the flipflop a couple of times due to ringing. However some like -Write Clock Phase B or -Sector Marker are going to be a problem if we see false transitions. 

I want the signals that arrive at the SLT input pins to be far enough from transition points or invalid voltage levels that I minimize the chance that ringing yields a transition glitch. A voltage produced by the terminator that is too low for logic high input lowers the junction voltage of the SLT inverter gate above too close to the cutoff for the transistor. A voltage that is too high above 0 for logic low input or sinks too close to 1.5ma current is susceptible to partial conduction of the SLT transistor, creating downstream glitches such as I see in the logic analyzer trace. 

The V2315CF drive chip sinks the signal line to ground when the signal is logic low. The terminator resistors pull it up when it is logic high, but the SLT input gate interacts with that. There is current flow into the terminator from the SLT gate because of the +6V pullup inside the gate. 

POSSIBLE SIGNAL QUALITY FIXES

I realized that I could raise the voltage of logic high input even up to 5V, having no effect on the SLT gate detection of a logic high but reducing the current sinking into the terminator. There is no cap for SLT at the nominal +3V since current does not flow into the gate from +3V, it actually flows out at the delta voltage from the input pin and 5.7V. 

This leads to a choice to try a 110 ohm pullup resistor to the +5V rail of the V2315CF, no pulldown resistor at the terminator board, and observe the signals at both the input and output of the SLT gate producing the inverted -Sector Marker pulses. I will experiment with this.

The other design problem I have is the sharpness of the falling edge when the driver gate in the V2315CF switches to logic 0. The Lattice FPGA used in the V2315CF does not have the capability to lower drive current and slow down edges, so the edge going into the SN75451 driver chip is very sharp. Some ringing is caused by the very sharp edge. I can minimize it by adding a series resistor to the output line to lower the current flow, however that quickly interfees with the strategy of using a 110ohm pullup, as any resistance much above 10 ohms will cause the SLT gate to fail to see logic low because of the voltage divider between the 110 pullup and the series resistor. 

I would need to slow down the signal elsewhere, perhaps in the path between the FPGA and the 75451 chip input pin. However, clean options don't exist to do that as rework on an existing board. The gerbers show that the signal line runs under the chip on the top layer and then runs in a tight group with very little spacing on the bottom layer. I highlighted the traces and circled the input pins on the 75451.

I am hoping that good impedance matching and the 110 ohm pullup will clean up the signal suitably to avoid any false transitions. I believe this will generate about 1ma of current between the +5V supply of the V2315CF and the 1130's +3V rail, assuming that the circuitry in the 2310 disk drive uses a 750 ohm pullup resistor on its output, when we are in real mode. In virtual mode, the disk drive circuit is isolated from the V2315CF.