Wednesday, May 13, 2015

Logic cleanup and micro-testing of the SAC Interface Box functionality


My reset signal was generated by the USB mechanism and process, thus it was emitted synchronously to the clock edge. By using that for async resets of my other FSMs, I wasn't meeting the setup requirements. Switching to synchronous reset flipflops ensured that the FSM came out of reset on the next clock edge after the reset signal went down.

Testing continued after I returned from my regular Wednesday midday time at Computer History Museum meeting with the other 1401 restoration team members. Many of the small issues on my 'punch list', to borrow a term from home construction, are resolved. However, there is still a weakness in the interaction when I am pumping a large core file down to store into the 1131 memory, where the FSMs sometimes get out of sync.

I am going to noodle on this a bit, set up some more precise instrumentation for the logic analyzer, but also consider restructuring the logic to merge some FSMs as a way of ensuring tighter coordination. The downside to combining FSMs is they get complex and less easy to understand, compared to modularizing the requirements into many simple FSMs.

The simple FSM is easier to debug and make solid, but then interactions among the machines becomes more complicated. A single large FSM has no difficulty keeping everything in sync but becomes so unwieldy that achieving correct operation gets much harder. A design tradeoff.

I have to be 101% convinced that the SAC Interface Box is glitch free and working perfectly, since so many peripherals and functions will be layered atop it. It may seem obsessive to spend so much time and fuss over esthetics of the logic and its behavior, but that is how I am going proceed.

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