My last few cleanups look very good - initial tests all are free of any glitches or potential problem areas. I decided to run several more extensive tests just to ensure it all works right. The issues so far haven't required use of the logic analyzer, they can be spotted and corrected simply from symptoms, behaviors, and indicator lights.
The virtual card reader, last card and hopper empty function is now working exactly as intended, plus of course reading of cards into core. It was very important that I get the interaction between PC side program and fpga just right, something I feel good about. I can set up a program loop on the 1130 to read cards and then clear the condition in an interrupt routine, to which I would submit files that were decks of many cards.
It ran through the cards at about the speed of a 2501 reader, stopping when the virtual hopper went empty, then restarting when I opened the next file, the equivalent of loading the next block of cards into the hopper. My checkbox for 'last card' allowed the final card in the file to be read and the DSW properly recorded the last card bit for that case.
Loading simulator core files into memory is working okay but not signed off yet. I added a feature that makes a verification of the contents after loading them to memory to ensure the data is correct. The core load operation is almost right - close, very close.
However, I see sporadic issues with cycle steal writes, both in delivering card columns and in loading core, which I have to clean up before I can declare the job done. I think it might be timing, but this might take the logic analyzer and perhaps an oscilloscope on the 1131 to really see what is happening.
When I get the SAC Interface Box to my satisfaction, the next work is to build out the SPI links to the slave fpga and microcontroller boards that support all the input and output signals to the physical peripherals - for example paper tape, plotter, disk drives, 9 track tape drives, and an APL terminal.