PERTEC D3422 DRIVE RESTORATION
Testing resumed at midday on the Pertec controller logic. I don't know why I tied the counter chip reset to ground, since it resets on positive signals. I guess I thought they were inverted reset lines. Swapped the line from ground to +5 and now the timer is okay.
I did however pick up the correct chips and have carefully removed the existing chips and installed sockets, into which I will place the new 7400 and 7493 chips once I validate that I have everything properly hooked up.
To improve my instrumentation, I set up some 'registers' that I can look at from the PC, which show me the state of all the FSMs and key signals inside the machine. I keep a pair of registers for each set of signals - one is the current, instantaneous value and the other shows me if that FSM state or signal value has been reached anytime since I reset the fpga board.
It has already paid off in flagging conditions which shouldn't occur but that I might not have suspected enough to bring out on the four LEDs and four dynamic pins for investigation on the scope.
The seek transactional logic is nice and solid, but my sector read and display isn't right yet. I see the write enable signal which would store data words in the FIFO. I see the reset at the start of the read. However, it seems to stay at a count of zero. I need to be scoping the movement through various states to figure out what is going wrong.
Since it was late and testing was over, I was looking at the design to see whether I saw any errors or vulnerabilities. There are several separate state machines that interact, triggering others or waiting at key points to synchronize with another. I came up with a way to pull everything together into a single state machine, which will eliminate some risks and complications. I think it will be much more straightforward and as a result it should be more reliable.
NIXIE AND DEKATRON TUBE CLOCK
I received some of the parts to get my clock back in operating mode. I should have the last part in three or four days.