Monday, July 20, 2015

Pertec drive solenoid working, spins up to Ready status, now I build test controller to validate operation


The new fuseholder is working fine and I have normal power supplied to the logic boards. I went back to troubleshooting the solenoid lock behavior and safe status signal to the +5V Timer board. Exactly as I suspected the power transistor Q42 was blown. A roundtrip drive to Anchor Electronics netted me a few of those components.

After replacing the transistor, the solenoid snapped open and closed as it should. As well, the +5V timer board did its thing - after roughly six minutes of inactivity, the relay snapped closed and the lamps extinguished on the drive (other than the main on/off switch light which is powered by the nonswitched 5V from the timer board. A push of the start/stop switch turns the power back on.

I then did another spin-up and let the heads load, just to see whether the logic would advance to Ready status now. Initially it didn't, but it was a quick fix to get the drive to go ready each time it was started up. The status and sequence logic appears to be working properly.

My expectation is that most components are working correctly, which warrants further work on the drive. I dressed all the cables with cable ties to neaten up everything in preparation for the next phase of testing. I have a six foot work table that I want to place the drive on, but due to its high weight I have to wait until I have a few friends here to lend a hand.

Now to whip up an interface to a spare Nexys2 FPGA board and use it as a controller to test the servo operation. Once I feel comfortable that the arm is moving properly and under interface control, it will be time to begin reading from the pack.

The terminology for the interface is that a true condition is a low logic level, 0V, while a false condition is high level (+3V). This can be thought of as inverted logic, but some usage can be confusing. For example, where the documentation mentions that some events occur at the trailing edge of a signal, that means the positive going edge since the pulse is an inverted signal dropping to zero for a short period.

Pertec is mostly consistent with this approach, except for the data and clock signals that are emitted during reading. In the case of clock pulses, the time to examine the data signal is while the clock is high, not low. A clock begins with a drop to zero, beginning a bit cell, then when it swings back to high is the time when the data value is read - not just at the 'trailing edge' of the clock but during the interval while it is high.

I developed a plan for the use of the 8 slide switches, four pushbuttons, eight LEDs and four 7-segment display digits, and blocked out the basic timing I needed for the interface. I haven't yet allocated the specific IO pins and connections I will need, but I expect to work on this tonight and tomorrow.

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