Wednesday, August 5, 2015

Looking into automated wiring discover for 1401 systems


I went back to the drive to look at the condition of the head, prior to dismounting it, to assess what chance there was that the head is only a bit streaked with oxide but otherwise usable after cleaning. It looks very unlikely.

I used my 99% isopropyl alcohol to clean the head a bit, but it still had a very bad looking streak from the recording gap back to the trailing edge. It is likely something impacted in the head gap. There might be a chance, once I remove it to work on it more, but my assessment is that I need a replacement head.

I closed up the drive for the time being - if I can figure out which disk generations are similar - 100 tracks per inch and 200 bits per inch at 125 microinch flying height and 2400 RPM operation - I can probably find a replacement head for one of those and make it fit. I am too bummed to pull the heads yet.


Working on the Connecticut 1401 system at Computer History Museum flagged some wiring that is not reflected in the ALDs - our only documentation. Further, there are scattered white, red and blue wires used on the backplane, where IBM would have only used yellow. Keeping the system operational depends on accurate documentation.

I began thinking of a practical way to determine the wiring as it sits. The machine has 20+ gates of SMS logic cards, with a backplane that is six columns wide and 26 rows deep. Each of those 156 card slots has 16 pins that are wrapped with wire that snakes among all the slots.

Using a continuity tester (with the cards removed), would involve somewhere between 500,000 and 800,000 combinations of two pins (ignoring the pins that feed power and ground to the cards) per gate. Remembering all past connections reduces the search space, but not enough to make it practical to do manually at 1s per test. Probably six full time days per gate.

In addition to the intergate wiring, there are cables that carry signals between gates and of course to some connectors for cabling to the peripherals. The number of signals on a gate that are carried to other destinations might be 300 on a typical gate, which still leaves a lot of testing to find the other ends.

I had an idea of a way to automate some of the searching. I imagined a board that was the same size as the backplane on a gate, with 2080 spring loaded plates that would make contact with all the backplane pins when the board was pressed into place.

With just a few hundred chips, I could create circuitry that would allow an Arduino to select any pin to provide testing power and then probe all the remaining pins to find those with continuity. It would mark all discovered pins to eliminate them from further searching, and it could do this at a high enough rate that the entire wiring of the backplane would be extracted in just a few minutes. Therefore, backplane mapping of the complete machine can be done in about one hour.

The cables that run off each gate can be traced by injecting a high frequency oscillation on the relevant pins of the gate, which can be followed by using a probe as an amplifier, following whee the signal is strong until the other end is discovered. This is more labor intensive. If a few people were stationed with antenna/probes around the machine, we could probably find the remote end of each signal in a half minute. That requires 150 minutes per gate or roughly one day to document them all.

This allows us to use the discovered information as a cross check when debugging from the ALDs, as we can look up the net attached to any pin and see where the signal is connected. If the ALD is missing connections, we will know and can respond appropriately.

The database could be mined to produce alternative ALDs, by entering the circuit type, input and output pins of the card in each slot, so that the gates can have the attached networks all listed in our own automated diagrams.

It would probably cost around $350-500 to build the tester board for the automated discovery, including the spring loaded plates that contact the backplane. The first version I thought of would use CD74HC4067 chips, which are bidirectional 16 x 1 analog switches. Thus, a pair of these chips would serve each of the 156 card slots on the backplane.

These chips have selection lines and a master enable - the selection lines for all 156 of the 'input' chips are the same, since the enable pin selects which is activated. The selection lines for the 156 output chips are also the same, with the enable pin doing the activation of only 1 of the 156 at a time.

The 312 enable lines can be addressed by a row and column selection, thus 6 x 26 lines, times two. 5 bits each for input and output rows, 3 bits each for for input and output column, plus the input line that the arduino will sense. 19 pins are well within the scope of the low cost Arduino boards. The arduino could use another pin to toggle the output bus between a steady logic level for net discovery and a high frequency signal to trace off-gate lines.

I will fill out the design and raise it with the other team members to see if it is interesting to pursue.

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