As I am away from home attending the Intel Developers Conference, I had limited access to the project. I did make progress on the medium speed SPI link protocol, which transfers 64 signals each way between the microcontroller based slave device and my master unit. With the VHDL essentially completed for the FPGA side, but not tested, I put in some time finalizing the Arduino implementation for the slave unit.
Wednesday, August 19, 2015
Away but making a bit of progress with FPGA design
SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130
As I am away from home attending the Intel Developers Conference, I had limited access to the project. I did make progress on the medium speed SPI link protocol, which transfers 64 signals each way between the microcontroller based slave device and my master unit. With the VHDL essentially completed for the FPGA side, but not tested, I put in some time finalizing the Arduino implementation for the slave unit.
As I am away from home attending the Intel Developers Conference, I had limited access to the project. I did make progress on the medium speed SPI link protocol, which transfers 64 signals each way between the microcontroller based slave device and my master unit. With the VHDL essentially completed for the FPGA side, but not tested, I put in some time finalizing the Arduino implementation for the slave unit.
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