I had a board meeting today, but eventually got out to the workshop and resumed testing. First I tried my new mirror buffer logic in the fpga to allow the devices on the 1130 to go full speed, capturing any data into a 1K word buffer in the fpga for extraction by the mirror device adapter code running on the PC.
I began to write and read to the FIFO but had some problems that need fixing. I also did more testing of the virtual 2310 disk drive adapter, cleaning up a few behaviors. Not sure how much time I will get over the next few days - very heavy work schedule ahead - but even 30 minutes at a time helps move the project forward.