Building out and testing the write sector logic

Relatives joined us today at poolside, requiring my presence and shortchanging the disk tool effort. I still managed to achieve solid progress in the time before and after their visit.

XEROX ALTO - DIABLO DISK TOOL CREATION

I set up a quick simulation of the writing FSM, which should be producing transitions for the right mix of clock and data values, which took a little bit of fussing with simulator stimuli but eventually gave me a good insight into how this was working.

I did some tweaking and got the timing just right - transitions exactly as they should occur. Next up is to write and test the serializer FSM, which will take a word given to it and feed the 16 bits to the write FSM one at a time as the 'getbit' signal comes from that write task.

The simulator helped me get the serializer working properly with the write FSM, so that I could then pop up a level and build the write field FSM that uses them. Soon they were working together well, once I stuck in a bit of glue logic to control when the new word is loaded into the serializer.

The write field logic has to step through several phases as it writes a record:

1. write a selected count of words of zero (the preamble)
2. write a sync word "0000000000000001"
3. write a selected count of data words, XORing the contents to form a checksum
4. write the checksum word
5. write four words of zero (the postamble)

For the first (header) record, the preamble is 34 words long and the data field is 2 words long. The label record has a preamble of 5 words and a data count of 8 words. The final record, data, has a preamble of 5 words and a data count of 256 words.

When writing records, I will have to seamlessly transition from one call of the write field to the next, ensuring that the postamble words of one field and the preamble words of the next record are contiguous. This will be a constraint on the next higher level FSM, write sector, which will invoke the write record FSM three times.

The write field FSM was written in a compact style I have developed, minimizing cycles but making the logic harder to write and understand.