XEROX ALTO - DIABLO DISK TOOL CREATION
Here is the signal timing chart that my state machine should be producing.
|RAM protocol for pseudo-static read/write|
Once I know that I can read and write RAM properly, I will move on to replacing the Digilent utility code used to move files between PC and RAM. Tested the FSMs until I got this right. All was good thus begin reintegrating the utility access logic.
The main discovery I made today is that coding VHDL while feverish is not a good idea. I wrote "if signalx <= '1' then" several times, when it should have been "if signalx = '1' then". No error from the toolchain, but results in an assignment of '1' to the signal and an always-true condition for the if statement, not what I wanted at all.
Using the eight LEDs on the board, I displayed the top half of the word last read from memory, which matched the last data word of the disk sector emitted by my internal pattern generator. The problem is that I should not be doing any read of memory when reading the sector, everything should be a write.
This is a clue of a potential flaw somewhere, essentially a weakness in my logic for choosing when to write versus read. I made some improvements and tested more. The spurious output of data was resolved, but still not seeing data through the Adept utility.
At this point, going to recode the logic myself, leveraging my working memory access FSM. Setting up the FSMs for reading and writing the registers, particularly registers 9, 10 and 11, being the RAM address, was easy. More work was implementing the transactional "handshake" for the read or write to the automatic register 14.
I was still working on it by the end of Saturday, still going through bouts of fever but gradually getting better. Tomorrow I will finish up the utility access to my RAM read/write machine, test it and hopefully be ready to read disk contents in the afternoon.