Checking instructions and edge cases by hand - everything worked as it should

INSTRUCTION SET NOT THAT LARGE BUT VARIANTS INCREASE THE NUMBER TO TRY

The instruction operation code (opcode) field is only five bits, thus 32 unique codes are possible of which 24 are assigned. However, there are two modifier bits that expand the number for a few - mostly the shift instructions. In addition, we have the short versus long (one word versus two) formats where instructions behave differently based on length, and some that vary their results when index registers are selected. 

Mostly the instruction process is common to all instructions. The first memory cycle is I1, fetching the first word. Long format has a second fetch cycle, I2, to grab the second word. Indexed instructions have a third memory cycle, IX, to read/update the index register. Indirect instructions take an extra memory cycle, IA, to get the contents of an address after the I1/I2/IX have finished. 

At the end, there are execution cycles, E1 for almost all, E2 and sometimes even an E3 cycle in the case of XIO Read, XIO Write, or the XIO Sense instructions. Some instructions, such as branching instructions, don't take an E1 cycle because they have already updated the next instruction address (IAR) at the end of their I1/I2/IX/IA cycles. 

Once you verify that use of an index register does make use of the core locations 1, 2 or 3 as the index register, it will apply to all indexed instructions. Once you verify that a long format fetch will pull the target address from the second word, all long instructions will fetch properly. Same with indirect (IA). 

The function of the instruction is more individualized and needs checking. That is, what you do with an address that was generated or an index registers contents will depend on the instruction that was coded. Also, the E2 execution cycle of many XIO instructions may inhibit fetching from memory since the device controller injects data as if it came from memory - XIO Sense Device or XIO Read are examples of this. 

These are the Op Codes for the IBM 1130:

• Load - 11000
• Load Doubleword - 11001
• Store - 11010
• Store Doubleword - 11011
• Load Index - 01100
• Store Index - 01101
• Load Status - 00100
• Store Status - 00101
• Add - 10000
• Add Doubleword - 10001
• Subtract - 10010
• Subtract Doubleword - 10011
• Multiply - 10100
• Divide - 10101
• Logical AND - 11100
• Logical OR - 11101
• Logical Exclusive OR - 11110
• Shift Left - 00010
• Shift Left Accumulator only - bits 8/9 are 00
• Shift Left Accumulator and Extension - bits 8/9 are 10
• Shift Left and Count Accumulator only - bits 8/9 are 01
• Shift Left and Count ACC and Ext - bits 8/9 are 11
• Shift Right - 00011
• Shift Right Accumulator only - bits 8/9 are 00
• Shift Right Accumulator and Extension - bits 8/9 are 10
• Rotate Right Acc and Ext - bits 8/9 are 01
• Shift Right Accumulator only - bits 8/9 are 11 (duplicate of 00)
• Branch or Skip on Condition - 01001
• Normal if bit 9 is 0
• Switch off current interrupt level on branch if bit 9 is 1
• Branch and Store IAR - 01000
• Modify Index and Skip - 01110
• Execute Input Output - 00001
• Wait - 00110 
• Implied Wait - 00000 one of eight unassigned op code values
• Implied Wait - 00111 one of eight unassigned op code values
• Implied Wait - 01010 one of eight unassigned op code values
• Implied Wait - 01011 one of eight unassigned op code values
• Implied Wait - 01111 one of eight unassigned op code values
• Implied Wait - 10110 one of eight unassigned op code values
• Implied Wait - 10111 one of eight unassigned op code values
• Implied Wait - 11111 one of eight unassigned op code values

CHECKING EDGE CASES FOR RESULTS

Arithmetic operations need to be checked for cases such as different signs, both signs negative, overflow, underflow and carry status. These are in addition to basic checking, e.g. that addition works, AND works, etc. 

Branch conditional instructions must be checked to see that they properly interpret the conditions:

• ACC is zero - bit 10
• Acc is negative - bit 11
• Acc is nonzero positive - bit 12
• Acc contents are even - bit 13
• Carry indicator is off - bit 14
• Overflow indicator is off - bit 15

Depending on whether the BSC is short or long format, it either branches when ANY of the conditions selected by bits 10-15 are true or branches when NONE of the selected conditions are true. The BSI long format instruction also does its branch selectively, if NONE of the selected conditions bits 10-15 are true. The MDX instruction updates the next instruction address, an index register, or a memory word depending on its format. That is:

• Long format with no index register will add bits 8-15 of first word of instruction to the memory location
• Long format with index register adds number from memory to the selected index register
• Short with no index register modifies the next instruction address by bits 8-15 (signed value)
• Short with index register adds signed bits 8-15 to the index register
• If the result of addition is zero or negative, skip next instruction except short format no index register does not skip ever

As you can see, the MDX is a complex little beast and thus all the variations needed to be tested to be sure it was working properly. 

The Load Index instruction has less complexity, but it will either put a value in an index register or if no index register is specified, it simply makes that value be the content of the IAR, the next sequential instruction thus is a branch. Note that it simply puts bit 8-15 of the first instruction word into the register or IAR, it does not modify the contents of IX or IAR by that value. Thus this short format instruction can only load a value of -128 to +127 or branch to one of those addresses while the long format can branch anywhere and load any possible 16 bit value to the register. 

The status indicators, carry and overflow, are set and reset under somewhat complicated situations. They are mainly generated by arithmetic operations, but also by Load Status. Some instructions reset one or both, others leave them alone. I have to test that many of these situations work properly.

RESULTS OF MY TESTING WERE EXCELLENT

Every instruction and edge case that I tested worked exactly as it should. This is an excellent sign for the overall health of this system and indications that I can turn my restoration focus on the remaining two peripherals - console printer and internal disk drive.  I did attempt one of the diagnostic routines in the maintenance listings which involved setting all storage to a fixed pattern of 33FF which is a wait instruction , then running a short list of instructions loaded through the console entry switches.

The documentation says to run it and if the machine stops in a wait, some data path didn't work properly resulting in the incorrect branch. Indeed this machine stopped but I couldn't see why or how it would work properly.

I moved to the IBM Simulator, loaded storage with 33FF and loaded the simple list of instructions. It too stopped at exactly the same place with the wait. I suspect this code, which is in an appendix in a maintenance program listing, is not correct or perhaps I am missing some important instruction for how to run it. I will disregard this since I don't see anything failing in my testing. I even stepped through the same format of a BSI Indirect instruction and verified that it did work as it should.