Developing the HPS to FPGA lite signaling path

STRUCTURE OF THE CYCLONE V CHIP ON MY DE10-NANO BOARD

The Altera/Intel Cyclone V chip consists of two sides - Field Programmable Gate Array (FPGA) and Hard Processor System (HPS). The HPS side is a processor with dual Cortex-A9 ARM cores which may run a version of Linux. It has 1GB of DRAM and plenty of peripherals. The FPGA side contains 110K configurable logic elements along with PLLs and other features common to modern FPGA devices. This too has its own rich set of peripheral connections. 

The two sides, HPS and FPGA, can communicate using bridges that are engineered on the chip to support communications between the halves. These are fast and flexible AXI interconnects, which have a controlling and a controlled (previously master and slave) end. The chip offers three bridges, HPS to FPGA, FPGA to HPS and a lite HPS to FPGA version. For these, the first name is the controlling side which initiates all transactions across that bridge. 

The HPS side of the bridges are linked into the ARM level 3 interconnect. Thus instructions running on the Linux side can emit transactions over to the FPGA side on one bridge, the FPGA side can emit transactions over to the ARM system on the second bridge, and instructions on the Linux side can send transactions over the lite bridge which is the third type on the Cyclone V chip. 

MY INTENDED USE OF BRIDGES

I will use only two of the three bridges for my project. These are the FPGA to HPS bridge and the HPS-FPGA Lite bridge. 

The HPS to FPGA Lite bridge will send over the start address in Linux memory of the memory mapped virtual 2315 cartridge file, or it will send over an address of zero to indicate that no virtual cartridge is currently spinning. 

The FPGA to HPS bridge will be used to access memory in the Linux system, which is how the data words of our disk drive are read and written. The FPGA logic grabs each word from the HPS side as the disk model logic determines it is time to begin emitting pulses into the disk drive read electronics to let the disk controller and IBM 1130 computer read data from its virtual disk cartridge. When the disk controller is writing words to the disk drive, we capture those, build up each word and write it onto the HPS side using the same bridge. 

FIRST SECTION BEING CODED AND TESTED IS THE LITE BRIDGE TRAFFIC

The Linux side only has to send transactions with a memory address or with a zero address depending on whether a virtual cartridge file is spinning and ready to be accessed. Eventually this will take place when the Pick signal is activated or dropped, with a user interface allowing an operator to have selected which of a number of virtual cartridge images on the SD card that they have 'mounted' into the 1130 disk drive. 

Initially I will just code up a single transaction to send a known memory address to the FPGA side. The goal is to have successful transmission of that message to the FPGA and proper reception and decoding on that side. Thus my first side is a teeny bit of code for the Linux system and some logic in the FPGA to receive the address. I will find a way to easily the results of testing so that I can verify it works on a real board, once I complete all the simulation testing of my FPGA side logic.