Setting up for verification of capture of data written by 1130 disk controller

BASIC SCHEME FOR CAPTURE OF DISK WRITES

The disk controller writes both clocking signals and data pulses to the disk drive when a write is active, signaled by the assertion of the WriteGate signal. The clock consists of sequences of 720 ns long pulses as phase A and phase B. Phase A is the interval when clock pulses are written on the disk and phase B is used to write a pulse if the data bit value is 1 else no pulse is sent.

The controller will begin the preamble of about 250 microseconds of zero data bits. That is, we have pulses on the WriteDataBit line during clock phase A but nothing during clock phase B times. This is used by the reading circuitry of a disk drive to align its data separator. That circuit in the drive routes some pulses out the ReadClock line and others out the ReadData line, based on whether they are occurring during the clock (phase A period) and the data (phase B) times. 

I will recognize this unambiguously because the disk controller sends the phase A and phase B signals along with the WriteDataBit pulses. Thus I don't need to do anything special to align with the clock versus data periods. My state machine just follows the signals of the two phases so that I know when a pulse arrives in the data (B) phase, it is time to move on to the sync word part of the sector. 

The sync word is the pattern 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 and this is what tells the disk controller reading the sector later where the breaks are between words in what is otherwise an undifferentiated stream of bits. After the end of the sync word, we know that the following bit cell is the beginning of word 1 of the sector and that every 20 bit cells after is the start of the next word. 

I will need to spot a pulse arriving in a data period (phase B), then cycle through three more data pulses and one phase B with no pulse to arrive at the beginning of the first word coming from the disk controller. My state machine will advance through the four 1 bits and the subsequent 0 bits, matching this exact sequence and going into an error state if the data values vary from 11110. 

My state machine will proceed into a loop of up to 321 words of data capture. For each word, we detect and shift in the sixteen bits of the transmitted word, while accumulating a count of 1 bits we have seen. Based on the count of 1 bits, we then detect and match the corresponding error detection code of four bitcells. The possible values we will see are 0000, 1000, 1100, or 1110 with any other pattern representing an error. 

After we shift in the 16 bits of a word and verify its error code is good, we will emit the write request along with the data word; this is passed to another module which writes that data word in the appropriate RAM location over on the ARM/linux side of the board. 

If I detect an error, either because the sync word pattern isn't correct or because the error code doesn't match what is sent by the disk controller, I trigger the disk drive into an error state. It no longer responds to commands and must be power cycled to resume operation. 

SIMULATION TESTBENCH TO PROVE OUT THE WRITE CAPTURE LOGIC

I used the testbench to produce the correct phase A and phase B clock signals once WriteGate is asserted, then injected various pulses on WriteDataBit to validate my state machine and functionality. A text file will let me feed various patterns of bits to the state machine. I will use this to verify that I deal properly with minor shifts in timing, such as a preamble that is not exactly 250 microseconds long. 

The file will also let me attempt both correct and improperly formatted sync words, along with data words that have both correct and incorrect error detection codes.