REFINING THE DESIGN FURTHER

HANDLING THE UNLOAD OF CARTRIDGE

The control pattern of the bridges offered between the Hard Processor System (HPS) and Field Programmable Gate Array (FPGA) sides of the Cyclone V System on a Chip (SoC) is absolute dictator to vassal, formerly know as m**ter-s**ve where the M side is the initiator of all transactions. There is no way for the S side to wait with a read pending until the M side writes data. 

The S side will see a control signal go high to tell it that it must respond to a read or write, otherwise it must do nothing. The design challenge with the prior approach where I would fetch the data from SDRAM by reading on the F2SDRAM interface then write that data back on the H2F link is that the M side decides when to do a read of the word I am ready to write and it isn't synchronized with my SDRAM reading activity. I can't tell it to wait, the M side will determine when it asks for that word and I better have it ready.

Instead, I am setting up an embedded RAM on the FPGA side which will hold an eighth of the cartridge file at a time. When doing an unload, I will fill the ram with the 65, 536 words then respond to a status interrogation being repeated from Linux that it is time for the master to loop and read those words and store them in the memory mapped virtual cartridge file. A continue command on the H2FLW channel tells us to read the next eighth of the data from SDRAM into the embedded ram buffer, after which we tell the HPS side it is time to fetch those.