Working my way down through the toolchain and identifying areas for further study

TOOLCHAIN IS THREE SEPARATE PARTS

The toolchain can be grossly divided into three portions that are used to design and debug projects on the Terasic DE10-Nano and other boards using Intel/Altera System on a Chip (SOC) components. These are Quartus,  Qsys and System Builder.

QUARTUS IS LIKE VIVADO AND OTHER FPGA SYNTHESIS AND SIMULATION TOOLS

Quartus is the tool focused on the FPGA side on the chip, where high level language inputs define the logic and functionality. These are synthesized and then can be implemented, producing a bit stream to load into the chip to instantiate the functionality desired. It provides a simulation capability to test out logic design. There is a large library of existing intellectual property (IP) which are functions that can be introduced into a project to provide functionality that otherwise might need to be designed from bare metal upwards. 

QSYS IS SPECIFIC TO THE SYSTEM ON CHIP COMPONENT

Qsys deals with the unique nature of an SOC, which has portions of the chip whose logic and structure are fixed and immutable, with others like a standard FPGA. The SOC chip has both a fixed hard processor system (HPS) which is a computing system based on ARM processors, and FPGA logic that is customizable. 

The two sides, HPS and FPGA, are tied together by various signals and interface circuits. Qsys is concerned with this level of the chip - the interconnections with the HPS and also the integration of both IP and user written FPGA logic.

Qsys rather uniquely presents a graphical view of the various control signals going into and coming out of each bit of logic - IP, HPS, SOC specific interfaces and user logic modules. Mouse clicks can cause these to be connected as desired, plus the detailed parameters for the bit of logic is configured at this point 

SYSTEM BUILDER IS A LAYER ABOVE QSYS WITH BOARD MAKER ORIENTED DETAILS

The Intel/Altera SOC chip, for example the Cyclone V used in my project, can be implemented on my own PCB or bought as part of various boards. One maker of boards, Terasic, produces a specific board that contains the Cyclone V SOC chip along with many useful adjunct devices. 

The Quartus tool set defines general FPGA logic, where look up tables and other elements of an FPGA are configured and interconnected to instantiate the logical functionality being designed. The Qsys tool adds recognition of the HPS side and the integration circuits between HPS and FPGA. However, neither of them have any idea what RAM, ethernet or other chips were placed on the DE10-Nano board by Terasic. 

The System Builder knows the external pins of the board and all the chip functions included on that board. It is used to pick which are going to be the used in a particular project and the output of this builder tool are the starting states for both Qsys and Quartus. 

DIGGING INTO QSYS

Now I understand the overall concepts and controls of Qsys (which is called the Platform Builder within Quartus because if the menu said Qsys it would be too easy to find). What I need to understand better are the interconnection specifics for the SOC chip and all the major IP elements that would be used to drive the SOC chip (and wider, to make use of other chips on the Terasic board). 

Intel and Terasic provide example projects along with the files to produce them, such as the "Golden Hardware Reference Design GHRD". One can follow along and implement the example project exactly or make small tweaks, but most of the understanding needed to accomplish more sophisticated projects does not come from those breezy introductory materials. 

Every YouTube video I have found about these Terasic DE SOC boards involves hobbyists following along with the example project and more or less implementing it without seeming to understand the depths behind it. The board is accessible to many hobbyists but only at this level. Take an example that blinks LEDs or communicates over Ethernet, hack it to your purposes, and the job is done. 

I need to understand this much more deeply. The details are available, but in multiple documents covering Qsys, Cyclone and other aspects, each may involve many hundreds of pages. The challenge here is going from the very superficial coverage of the examples down to the weeds of the details. Abstract concepts, gradually building into the myriad details, is the path I want to understand this SOC and board system. Unfortunately, I only seem to find the weeds and the fluff, not the explanatory manuals or videos or courses that bridge that gulf elegantly. 

The HPS component in Qsys, by itself, has many signals and a staggering number of parameters that have to be configured. I am recording the choices made in various example projects such as the GHRD but without understanding of what they are and why these choices were picked, I can't build general projects using the system. 

one of many configuration panels for HPS

I won't need total understanding in order to move forward with this specific project, but I need enough to know how to drive the bridge links between HPS and FPGA sides and to access specific memory over on the running Linux image on the HPS side. Much of this intercommunication works by memory mapped addressing, thus one has to build up the addressing scheme as well.