SUCCESSFUL SYNTHESIS, ROUTE, PLACE AND BIT GENERATION
This is a quick blog post to let everyone know that I was able, using the newly created Ubuntu virtual machine and newly installed Quartus Prime 22.1 toolchain, to complete a build of my logic for the FPGA and SoC side of the design. Finally!
NEXT STEPS
At this point I want to go over all the signal pathways between modules, to be sure that everything is linked as I intended. I will also carefully examine the messages produced in order to clean up things like unused signals or unintended latches.
Congratulations and whew!!!
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