Monday, December 22, 2014

SAC Interface communicating both ways with 1130, debugging proceeds steadily


I put in more time today hunting the elusive spring inside the mechanism, but still no sign of that rascal. I ran out of daylight, spare time and energy working on the SAC interface, so not too much time put in on the console printer or the keypunch interface.


I began installing the improved arc suppression design today, adding heavy duty ground lines to run back to the keypunch power supply. I haven't finished the zener diodes to clamp the input lines, nor have I hooked the ground wires into the main keypunch power supply, so no testing yet.


I triple checked the assignments of FPGA pin to signal, to connector pin, to interface board and so forth. I discovered that my spreadsheet that correlated the various pins on the breakout board to the 160 pin SAC cable to the logical signal to the fpga logical net name to the fpga chip pin was corrupted.

It took a while to carefully align everything for the driving circuits, but when I brought the box up after this adjustment, it reliably forced the processor into the chosen interrupt level (I used the two slide switches to request either IL4 or IL5; both worked properly).

I am adding a diagnostic mode where I can see the state of all the received signals quickly using the Adept register mode utility and some logic mode I added to the fpga. Otherwise, I had to make use of just two LEDs on the board to test out some 36 input signals, which would have been inordinately tedious to do with 18 recompiles of the logic and testing cycles.

I haven't yet figured out how to get my logic configuration into the flash ROM on the board so that it boots up correctly from ROM at power up. At the present, I have to jumper the AC relay to power up my box first, manually load the configuration into the FPGA, then power on the 1130. When I get the ROM boot working it will power itself up correctly with the current logic configuration.

SAC Interface box as it is tested, USB cable at top links to PC for configuration and test activities.
My box seems to work okay in a static environment, when the 1131 is paused at one of the T clock states (in SS mode), but in any other mode it quickly decides I am asking for all four interrupt levels and probably is sitting in a cycle steal loop. Likely this is a noise, induction or similar problem that I can diagnose with a logic analyzer or storage scope, once I get back to testing.

My diagnostic mode didn't work, but that was due to a flaw in my logic for that new functionality. I will correct it tonight in order that I have this information available for future testing.

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