Saturday, January 16, 2016

Working on other virtual peripheral functions of the SAC Interface Box


My changes to the 1130 simulator required me to split the logic to maintain two separate DSWs, since the way the utility works (and other utilities) is to issue certain XIO commands to both 1132 and 1403 printer addresses in order to determine the fastest printing device that is ready to print. With the split, the DCIP utility works perfectly in the simulator. I created a load file to use with the real 1130 system.

I next turned to the Python side code for the virtual 2501 card reader and virtual 1442 card reader/card punch devices. Armed with the lessons I have learned debugging the virtual disk, I scanned to see if the division of labor between PC and fpga needs to be changed for either of these functions.

I saw the same flaw with interrupt causing status bits in the DSW which need to be reset in the fpga, immediately upon an XIO Sense DSW with Reset, rather than up in the PC code. Both the 2501 and 1442 functions need this change.

In addition, the current 1442 function sends every level 0 interrupt for a card column up to the PC where a single column of data is sent back. This will be very slow and inefficient. I will rewrite the code to use 80 column buffers that are written or read by the PC as an entire virtual card, allowing all the detailed column by column stuff to be done fully in the fpga.

The way this will work is that the PC sees the XIO Control that does a start read or start punch or line feed, all things associated with the PC file which stands in for card decks. The PC will push down the card image to the fpga and trigger it to begin emitting the interrupts on level 0 that cause the program to issue XIO Read (or Write if punching) to move one column from the buffer.

The end of the read of a designated card image will be reflected in a pseudo XIO code to the PC program which is polling for this completion and pushes an op complete DSW, after which the fpga side handles the interrupt and sense DSW functions. For a punch, the fpga will not trigger op complete, instead waiting for the PC to extract the newly written card image from the buffer and then pushing down a DSW that fires off the op complete. A bit of logic to write in the fpga but should be fully interlocked.

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