Monday, August 29, 2016

Driver board tested okay, building driver logic now


I wired up the driver role extension board, powered it all up and began testing to see that my outputs would swing between 0 and +5 as I switched on each signal. I discovered that the signals for Cylinder Address 64 and Cylinder Address 128 were swapped,. I also discovered that my Index Marker, Read Clock and Read Data input signals were swapped around.

My solution to these was to adjust the documentation. I will then route them appropriately inside the FPGA and all will be well. It was time to add the layers of insulation and copper grounding plates to both sides and finalize this board for use.

I built up the logic to keep track of the current disk sector, watching the Index Marker and Sector Marker lines for pulses. Next, I built up the state machines to trigger a seek to a cylinder and a restore to home cylinder.

One design choice I made might get confusing as I work on my logic. The Diablo interface uses inverted logic, meaning that to activate a signal such as Restore, you set it to 0 while the inactive state is 1. Inputs are the same, with a Sector Marker signal staying at 1 except for a 5 microsecond period where it drops to 0 (active).

I invert all those signals at the entry/exit to my fpga, so that inside my logic, an active signal is 1. Thus, Sector Marker goes to 1 for a few microseconds. Restore is at 0 unless I want to request a restore, where I set the signal to 1 for a few microseconds.

This evening I added logic to match a specific sector target against the sector counter that is continuously running as the disk rotates. I finished with only a partial design for the main sector read FSM, which I have to break apart more modularly to leverage it better for the complex structure of a sector.

I am somewhat concerned that my level shifters are not fast enough for the Read Clock, Read Data and Write Data and Clock signals. I need to generate pulses with a rise time of <50ns and a duration of just 100ns, For the combined data and clock signal for writing, these occur every 320ns. The level shifters could be slower than 50ns for the pulse edges and will just barely fit two in the 320ns window.

I think I may need to come up with a manual circuit having a much faster transition time and frequency response. The FPGA itself produces great crisp signals, but at 3.3V not the 5V swing used for the Diablo drive. I think I have a fix for the outbound signal and can handle the inbound two signals with a voltage divider or zener diode.

At this point, I must get the register read/write and RAM read/write to work over USB, as that will be the key to the rest of the development.

No comments:

Post a Comment