IBM 1130 MRAM memory replacement - continuity test, then testing on the IBM 1130

CONTINUITY AND SOLDER JOINT TESTING

I found one pin that appeared to be soldered well but lacked continuity - the output of the write timer circuit. Based on this I decided to do a more thorough test using the PCBite probes to check that each pin on a chip had continuity to the appropriate end points and that there were no shorts to adjacent pins. This was time consuming but worthwhile.

I came across about ten connections that looked like shiny good joints and the pin wouldn't move when pushed sideways, but electrically they were capacitors or open circuits. I carefully repaired every one of them.

I took the time to check many of the control connections and the memory address lines for good continuity. Once I believed this was likely free of bad connections, I moved over to test with the 1130. 

LIVE TEST ON THE IBM 1130

I plugged the board into the IBM 1130 in place of the IBM core memory compartment B-C1, connecting cables T1, T3 and T4 as well as +12VDC power. The machine was powered up and I could do some quick tests. 

Using the rotary mode control set to Load and to Display, I can load chosen patterns into memory and read the results. The pattern is toggled with the 16 console entry switches (CES) and the results show on the display panel as the Storage Buffer Register output. dete

I saw a few spurious Parity Checks - which should never happen because the two parity check bits are created on the fly by my board based on the memory contents. Mostly the memory was storing the data I set on the CES and retrieving it when requested, but there were those phantom Parity Checks to consider. 

I then used the Storage Load and Storage Display functions that are available to the repair engineers - these let me set a pattern on CES and loop repeatedly through memory setting that into every word. Once done I could perform the Storage Display and loop repeatedly reading memory. During these events I found a few more phantom Parity Checks. 

More disturbingly, when I went back to use the rotary mode to display locations, after having set every word to FFFF, the data coming back was somewhat random, not the pattern. 

FIRST THEORY

I suspect this is a timing issue, because the detection of a parity check occurs during the write portion of a storage cycle, when the data should have been established along with its chosen parity by some logic in the CPU. It could also be a continuing issue with reliably triggering the B register flip flops with the sense output pulses. 

I will have to set up a logic analyzer to capture key signals while I run some Storage Load, regular load, Storage Display and regular fetches from memory locations. That will help me focus down on the area having problems. 

Side project - MV864A meter restoration - blocking out entire schematic

USING EXISTING MANUAL SCHEMATIC TO BLOCK OUT NON PCB PORTIONS

I chose to use the schematic in my manual, which is too modern to match the version of the meter I own, to block out the remaining functions most of which are not on the two printed circuit boards. This includes the Range Attenuator, the Function switch, the Meter, the input jacks, the zeroing pot for the meter and the pot to adjust the full scale resistance reading to 0. 

The components used for the Range Attenuator sit on the power supply PCB and are joined to the rotary switch via wiring. I used the manual version of the part numbers for the parts that will be on the power supply PCB for now. This is because the part numbers on the board don't match between the manual and the actual meter I own. As well, the numbering scheme for the rotary switch, function switch and other parts that are not on a PCB are different so I went with the manual initially.

I intend to trace out the actual meter to resolve all the numbering to match my actual meter. I will also catch any changes in the circuit that exists between the manual version and my schematic. I don't expect many differences in this part of the device but we shall see. 

NOT DONE WITH THE RANGE ATTENUATOR YET

I put in quite a few resistors and connections for the range attenuator but have not finished yet as it is tedious work with many parts that have to be wedged into the schematic around the rotary switch sections. I did complete the Function switch.

REMAINING WORK OTHER THAN RANGE ATTENUATOR AND MATCHING MY METER

I have to put in the output connector on the back that delivers a 0-1V output matching the meter deflection. The pot to zero the meter is not yet implemented. 

I then have to rationalize a connection from the Function switch to the power supply which in the version from my manual is passed a fixed current produced by the power supply. My reverse engineered power supply does not have a current source like this, so this will be a notable difference between the manual and my meter. The current is applied only in the resistance function to power the input jacks so that a voltage drop is generated on the resistor under test, which is then measured by the meter.

SCHEMATIC SO FAR

 

Side project - MV864A meter restoration - simulating the DC Modulator Driver that produces 94Hz chopper signal

TRYING TO TEST SECTION BY SECTION USING LTSPICE SIMULATION

I started with the circuit that should be oscillating at 94Hz, producing square waves on LEDs inside the photoisolator component. This part of the circuit is called the DC Modulator Driver.

The light from the LEDs falls on two variable resistance photocells in that component, which are biased by the input signal to the meter and then amplified. Ultimately, the meter will compare the output of the oscillator with the detected but biased signals to capture the results of the input. 

I found an error in my schematic but after correcting it, I was still unable to see oscillation of the circuit. The manual's schematic has a different design using silicon transistors rather than the germanium ones in the actual meter I am restoring. I captured the DC Modulator Driver circuit from the schematic in the manual but that too did not oscillate. If it had worked but my reverse engineered version did not, it would focus me on possible errors or inadequate modeling of the germanium semiconductor devices. 

Since neither works, I have to find the root cause of the failure. It may be some missing components inside the photoisolator component, which is a sealed can that the manual insists should only be serviced by Millivac. I do know that the meters work in real life. 

GETTING THE MORE MODERN VERSION IN THE MANUAL TO WORK

A mistake in drawing the circuit of the manual's version of the DC Modulator Driver caused it to produce the 94 Hz output I expected. I tied on side of the oscillator output to the bias voltage source, which caused the opposite leg to produce 94Hz. However, when I corrected the drawing the simulation once again flat-lined. 

That was a clue. Turns out the value of the inductance, the four resistors in the photoisolator component and the bias voltage setting on the pot are all inter-related and must be in certain ranges to achieve oscillation. 

GETTING MY REVERSE ENGINEERED SCHEMATIC TO WORK

I discovered that the signal transformer was quenching the oscillation - when I removed the transformer I got my 94Hz square waves but oscillation didn't happen with the coil in place. I don't have specifications for the coil that I had to take wild stabs at inductance to find a value that allowed the transistors to oscillate. 

It could be that the transistor model I used didn't have enough oomph to oscillate, since I also don't have specifications for the 2N1373 germanium transistors I found in my meter. Also lacking were the resistance values in the photoisolator and the LED characteristics. 

PASSED REASONABLENESS TEST

Since I could achieve oscillation with generation of the square waves with certain component values, plus knowing that the real meter works so it is definitely oscillating, I knew that the schematic I derived was now representative and correct. 

Construction of new 1130 MRAM memory board completed

BUILDING THE NEW BOARD

I used my hot air rework tool to remove the parts that were to be salvaged from the old board. These were still part of the design of the new board. For each, I removed it carefully and then soldered the part onto the new board. 

This included the gold pins that form the connector that the IBM 1130 cables are plugged onto. For this, I used the soldering iron and pushed the pin up a bit so that I could then grip it with pliers and remove it while heating again. I use a spare socket to push the pins into, ensuring the 24 pins are aligned properly when I solder them down to the new board. 

I examined the board closely with the microscope, pushed on leads to ensure a good bond for each pin to its pad, and did a few continuity tests including validating there was no short on the main power rails on the board. 

I had to return home to wait for a delivery (an area rug was cleaned by an outside service), but will attach and test on the 1130 system when I get back to the shop. 

PCBs and parts are on hand - beginning construction of new 1130MRAM board

EARLY ARRIVAL OF PCBS

The delivery estimate for the new version of the memory board was Friday afternoon, but I was pleasantly surprised to receive it early this afternoon (Thursday). That was the last part I was waiting for in order to build what is hopefully the final version of the board and put it into the IBM 1130 system. 

BEGAN BUILDING NEW BOARD, INVOLVING MOVING PARTS ACROSS FROM OLD BOARD

The design has some new parts on it, both in the power supply area and for the Sense bit output circuits. I first installed the power supply and checked its operation before installing the rest of the circuitry. It gave me a reliable 3.3V supply for my circuits and isolates the ground when power is not applied so that there is no back feed of voltage from a partially energized 1130 into my board. 

The bulk of the construction will take place tomorrow, but I was able to install two of the timer chips that produce an 80-100ns pulse delayed 800 ns from the trigger event of a write to memory. The timer chips are very small and a challenge to solder, but I got them on and validated good connectivity for each lead without any shorts to adjacent pins. 

Side project - MV864A restoration - substantial progress in reverse engineering

POWER SUPPLY SCHEMATIC VERIFIED WITH LTSPICE SIMULATION

I had some errors in the schematic I drew for the power supply, which I identified when I began simulating the power supply in LTSpice. I had to invent a few models for the germanium transistor and RA1 reference amplifier, as well as dropping everything from the main transformer back to the wall plug, then put some resistors as loads for the -14.5VDC, -6VDC and the AC supply for the power on lamp. 

The result is a high confidence schematic for the power supply:

MAIN BOARD CAPTURED IN A SCHEMATIC

My drawing of the main board components is done but I have not yet done LTSpice simulation of the sections to validate my work or spot errors. Simulating transformers is a bit hokey in LTSpice, particularly a schematic with five independent transformers most of which have center tapped windings. Instead, I will replace the transformers with voltage/signal sources and inductors as the output load so that I can watch each section perform its role. 

DRAWING THE RANGE ATTENUATOR AND FUNCTION SELECTION CIRCUITS

The range attenuator selects the proper range for the input voltage, current or resistance, with fifteen steps or levels. It is implemented with a complex rotary switch having eleven sections with fifteen contacts apiece. This switches resistors to reduce the input to a standard level that the rest of the circuit is designed to handle. 

The function selection circuit has six positions - off, + voltage, - voltage, +current, =current and ohms. This rotary switch has seven sections with six positions each. I am about halfway through the range attenuator capture at this point. 

WILL CAPTURE INTERCONNECTS BETWEEN BOARDS AND CONTROLS

There are quite a few wires that run from the rotary switch to the two PCBs - as the power supply PCB has many of the resistors on it that are part of the range attenuator, it has the most wires connected. There are also a number that run from the input jacks and the main PCB to the range attenuator. That will wrap up the work reverse engineering this meter. 

Side project - MV864A restoration - reverse engineering power supply section

 WAITING ON PCB AND PARTS TO RESUME MAINSTREAM 1130 ACTIVITIES

The 1130MRAM memory PCB is scheduled to arrive on October 10th and the new components will be here on the 8th. Until I have the new board ready to final testing on the 1130, it does not have working core memory. That is required to begin testing the 1132 printer and 2501 card reader controller logic as well as to resume testing of my virtual 2315 disk cartridge project. 

In the interim I will keep busy doing these side projects - the Millivac MV864A meter and the IBM 3278 terminal restorations for example. It was worth $28 to speed up the delivery of the PCB, since I am eager to work on the top priority 1130 restoration tasks. 

POWER SUPPLY VASTLY DIFFERENT FROM THE MANUAL AND SCHEMATIC

The manual shows a power supply with four silicon transistors, four diodes, a zener diode, an LED for the main power indicator and three test points to measure +8.5V, -6V and ground. The actual board in my meter has one transistor-like device plus a large germanium power transistor, two diodes, and an incandescent main power indicator. 

Even odder, the three test points I found, marked TP63, TP62, and ground, measure -14.5V, -6V and 0V respectively. There is an 8.5V delta between the first two, but nothing shows up as +8.5V. The meter appears to work, thus this must not be a result of failure in the supply. Rather this is likely due to the older germanium technology used on my meter versus the redesign with silicon semiconductors. 

CHALLENGES FINDING DATASHEETS FOR BOTH TRANSISTOR DEVICES

I have completely failed to find any data sheets for the MHT3030 power transistor, although it is almost certainly a germanium PNP device. I did find the smaller device, a General Electric RA-1, in an old GE manual found on the web. It is a compound device, four terminal, with a transistor plus a zener diode attached to the transistor emitter. It was used in voltage regulator circuits and there are reference designs in the GE manual. 

This manual "GE Transistor Manual - Circuits, Applications, Characteristics, Theory" published in 1964 is a gold mine of information. The section on Regulated DC Supply and Inverter Circuits covers the Reference Amplifier (RA) devices and circuits using them to build 'precision' voltage regulators. Here is the sample circuit in the manual:

This corresponds extremely well with the recovered design from my reverse engineering. A few differences - the meter uses a half wave rectifier rather than the full wave design from the GE manual and the GE manual uses a fixed resistor voltage divider to provide the 7V reference voltage to the RA1 base when the output is (almost) 12V. 

Due to resistor tolerances and a more limited choice of resistor values in the 1960s, GE chose the resistors to give 11.73V which was the close enough (for a 'precision' voltage regulator). The inclusion of a potentiometer in the Millivac circuit allows for adjustment to hit a target output voltage, with the midpoint of the pot setting -14V and enough range to achieve -14.5V. 

Here is the schematic I created from reverse engineering the board of my meter:

Two things remain a mystery to me after this work. First, the method of creating -6V appears to be a simple voltage drop over 540 ohms of resistance - this only works out to an 8.5V delta if the current through the resistors is 15.7ma. Until I see how this line is connected on the other PCB I can't assess whether this makes sense.  Second, the existence of -14.5V and -6V rather than the +8.5V and -6V of the manual's power supply. 

Here is the schematic from the manual for comparison:

Side project - MV864A restoration - reverse engineering challenge

PICKED UP MILLIVAC MV864A AND PAID FOR MANUAL FROM THE MANUFACTURER

Having purchased a used high accuracy meter on eBay, it was time to restore and calibrate it so that I can use it on my bench. It generally works, but when I used my bench power supplies to deliver given voltages and currents to compare with the meter reading. The readings were close but not exactly on. 

This meter has a grid of potentiometers on the rear which allow for calibration of each scale of voltage, current and resistance. I found that on some ranges I couldn't get the meter all the way to the target reading even at the extreme of the pot movement. I also didn't know if I had to do the calibrations in a certain sequence or could adjust any scale independently of the others. 

I contacted Millivac and asked if I could buy the manual that has the schematic and calibration instructions. I provided the serial number of the unit to have them find the proper version of the manual. I was told that the oldest manual they could provide was for a newer version but that the schematics and other information should be quite close. I spent the $100 and began the restoration when it arrived - see earlier posts about this side project for details. 

MAJOR DISSONANCE BETWEEN MANUAL AND THE UNIT ON HAND

Unfortunately for me, the schematics and other diagrams are very different - you can see that the general scheme is the same but the parts used and layout were very, very different. The major reason is that my unit uses primarily germanium transistors whereas the manual shows the meter after they had re-engineered this around silicon transistors.

The parts numbers are all different, because it was a redesign. The layout on printed circuit boards is different. In order to put a scope or voltmeter on various points to compare against the values shown in the manual, you need to know where the point sits. Further, the waveforms and voltages likely have changed between the germanium and silicon designs. 

Here is the portion of the schematic that I have been reverse engineering - I still have a few values to add to the drawings and some cross checking, but it is close. First, the portion of the schematic from the manual. 

Next is the version I captured from the actual unit:

Lets zoom in one two sections to see how different they are. First we will look at the input filter that sharply notches powerline noise. Second we look at the preamplifier that finds the difference signal between the filtered input and a reference signal from the photocells of the chopper. 

For the input filter, I have the following component values and connections:

Compare that to the schematic portion from the manual. These parts should be very close since a notch filter has component values determined by the frequencies and rolloffs, which wouldn't depend on germanium versus silicon techology at all. In other words, this is the best situation for a match.

Even here we have a few discrepancies in the values of parts although most are close. The output resistance is much higher, which may be based on the change in transistor technology. The parts for the filter are visible on the board:

The variations would be tolerable here, even if I had to map out that 3R1 on the manual schematic is R201 on my PCB. Once I move into the areas where the redesign is more substantial, this becomes less feasible. 

The preamplifier as I found it on the unit has a germanium FET and two germanium 2N414 NPN transistors. 

The manual has a more complex circuit with the same FET but three silicon 2N2907 NPN transistors. I am guessing that they chose a lower gain for the three stages to achieve the same result as the two germanium transistors provided on my unit.

DIVERGENCE IS WIDENING AFTER THIS POINT

There are ten silicon transistors on the rest of the schematic and two coupling transformers in the version in the purchased manual. However, on the actual unit, there are fifteen silicon transistors and four coupling transformers. A second adjusting potentiometer is on my board, but not in the manual; it has no marking on the PCB to hint at its purpose. 

Here is the top of the PCB with the previously discussed sections partially covered to show the remaining components that must be reverse engineered. 

REVERSE ENGINEERING IS TEDIOUS BUT STRAIGHTFORWARD

The huge advantage I have is that the PCBs in the unit are single sided - traces only on the bottom and components only on the top. I have flipped the picture of the bottom so that I can match it to the parts in the top picture, allowing me to figure out the wiring between parts. 

I will keep at this until I have the entire schematic of this PCB captured. I figure I can use LT Spice to figure out the corresponding voltage and waveform values I should see at the reference points to correspond to the ones marked on the manual's schematic. 

In addition to this PCB, there is a second PCB that has the power supply and range attenuator components. This also is different from the manual version. Therefore I have to reverse engineer at least the power supply portion. The range attenuator and the front panel selector switch should match up fairly closely, so I won't bother drawing that out unless I run into problems during restoration that indicate a divergence. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 4

CHANGED SENSE OUTPUT DRIVER GATE TEMPORARILY

I am resigned to having to build another PCB in order to use a chip that has enough current sink capability to work with the 1130. I did set up components on a breadboard to redrive the signal for a couple of sense lines, to see if things work correctly with sufficient current sinking.

Since the current circuit is failing to set the B register, it is the same as when I store a 0 value for that bit. I will wire up the two check bits, as they must be on with an even parity such as all zeroes. I will also wire up bit 15 so that I can experiment with setting the word to either 0000 or 0001 which both should have correct parity when read back given the three circuits I will establish.

In order to use the existing board for this test, I just lifted the output pin of the three signals off of the 74HC03 chip where they were soldered. I can tack a wire to the pad and another to the lifted pin, interposing my ad hoc circuit between the two.

I used a 74HC04 inverter chip to convert the output of the 74HC03, an open collector that pulls to ground when the pulse should be generated, to a pulse that starts at 0V and goes up to the 3.3V level for a short period. This required a pull-up resistor on the input to the inverter, pulling it to 3.3V unless the open collector sinks down to ground for the pulse. The input to the inverter comes from the 74HC03 lifted output pin.

The output of the inverter was connected through a 720 ohm resistor to a 2n3904 NPN transistor. The emitter is connected to ground, the base connected through the 720 ohm resistor and the collector is hooked to the output for the -Sense bit line. This should be capable of sinking as much current as the SLT circuit can deliver - with the resistor I selected and the gain (beta) of the 2n3904, it could sink around 180ma which is why more than the 8-9ma I see in the LTSpice simulation as a minimum to flip and the 24ma it shows when the transistor is saturated. 

TESTING WITH LOAD AND DISPLAY MODE

I did a load of memory with all zero bits, then did a display. This should return all zeroes plus the two parity check bits at 1, for a good read. This worked as expected, no parity stop. The pulse coming back from the sense outputs to the B register were nice and strong. 

I then flipped bit 15 of the Console Entry Switches to 1 and loaded that value (x0001) to memory before doing another read. This should deliver x0001 to the 1130 with the first check bit at 1 and the second check bit at 0. That was exactly what I saw on the display panel and again no parity stop. The scope showed that the pulse was strong enough to definitively flip the B register bit on when we are outputting a pulse. 

B reg in purple set by sense pulse in blue

FIXING THE ISSUE PERMANENTLY

After I had validated the diagnosis that insufficient current sinking was the issue with the 74HC03 chips I had used on the prior design, I switched my design over to 74LCX38 chips that will sink 24ma per output, works on 3.3V VCC and is also a quad 2 input NAND open collector device. 

While an SOIC-14 version of the 74LCX38 is identical in footprint to the 74HC03, it is effectively unavailable so I had to switch to the smallest TSSOP footprint as even the intermediate SOP version was effectively unavailable. That required me to redo the PCB which I completed and sent off to JLCPCB on October 3rd. I also ordered the new chips and other parts from Digikey to build the new PCB, which should arrive before the PCB.

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 3

RESOLVED THE PIN ASSIGNMENT MISTAKE ON MY PCB

I installed jumper wires on the six pairs of pins I had previously identified. In addition, I discovered three more pairs that have the same characteristics - -Sense Bit 17, +SAR Bit 3 and +SAR Bit 10. Those were also jumpered on the backside of my board. 

TESTING WITH LOAD AND DISLAY MODE

I still saw parity errors when doing a DISPLAY on any address, but when watching the signals I could tell that I was in fact writing the 1 or 0 value into memory and then generating a pulse on the sense output line when the bit stored was a 1. 

However, B register bit was NOT being set when that pulse occurred, s it should. There is a flipflop in the B register circuitry that will be set if there is a falling edge on its input - that comes from my circuitry. 

THE ISSUE IS THE PULLDOWN CURRENT FROM MY BOARD (OR DURATION)

The sense output bit is generated by a 74HC03 gate, a NAND with open collector output where the gate pulls the output to ground when activated. The pulse may  not be long enough, at about 100 nanosecond duration, since the IBM core memory circuitry produces that pulse with a duration more like 180 ns. It is the falling edge that causes the action, not the duration, so that shouldn't matter. If it does, I could adjust it by swapping the capacitor that determines the length of the pulse I produce. 

However, what is more objectionable is the low point of the pulse I am producing. It is not down to zero volts, instead reaching no lower than about .6 volts which is way above the SLT logic zero definition. Since my gate is conducting to ground, I expected it to get much closer to 0V. 

Looking at the spec sheet for the 74HC03, it does show that with a 4.5V VCC (we are at 3.3V) and a 4ma current sunk by the gate at logic low, the voltage is typically .33V, which is already too high for SLT. As with all issue with digital logic, one has to look below the abstraction at the real analog behavior to understand why it is not switching. 

There has to be enough current to reverse the conduction of a pair of transistors at the heart of the flip-flop. This will depend on the resistors and other contributors to resistance as well as the current sink capability of the driving transistor in my gate. The flipflop is shown as consisting of several circuit elements in this IBM diagram below:

In the IBM documentation, circuit segments are named with codes such as T20SC, the first letter indicating the speed of the circuit which is 30ns in this case. The two digits define a logic function, then the suffix letters indicate the variant with differences such as resistor values used. I don't have a full set of schematics for these circuit segments but can find some (or close family members) in schematics I do have for certain SLT cards. 

This section of a 5804628 card schematic has a section where the only variance is in the two AND blocks which are S03AJ instead of S03SQ. 

The schematic for the T20xx circuits is:

The S03xx circuit attaches to one of the outer transistor collectors above such as pad 4 or 11.  On this card it uses an S03AJ circuit but we are more interested in the S03SQ which better matches our B register card. 

I then looked through other cards with flip-flops until I found the S03SQ circuit schematic on a 5803794 card:

Connector 2 above is what connects to the T20AB circuit connections to set or reset the flipflop. Connector 3 above is what connects to the output of the flipflop which blocks a set or reset from passing through if the flipflop is already in that state. Connector 6 above is the gate signal that sensitizes this circuit - when it is at logic low, a falling edge on connector 1 above will send a pulse to the flipflop. 

My board has to send a falling edge that will pull the charge from 33 pF capacitor, thus pulling down the base of a transistor in the flipflop, through a diode, causing it to conduct and flip the state. To clarify the discussion a bit, we are looking at the signals to set the flipflop when my sense bit pulse has a falling edge. 

SIMULATION TO UNDERSTAND CORRECT AND FAILING OPERATION

I set up LTSpice to simulate the circuit. I don't have exact parameters for the Germanium transistors and diodes in the IBM SLT modules, but I used a model I found for an old Germanium transistor and hoped the results would be reasonable. I set it up to be initially in the reset state and applied a 100ns pulse to the circuit on the set side at +1 second. The flipflop switched as I expected it to, seen in the graph below:

Green is Q, blue is notQ outputs of the FF

The circuit I entered is here:

I used an initial condition to set the flipflop to its correct starting state. I applied a pulse using a voltage source at the bottom and simulated to get the graph above. I can now experiment with various defects such as too high a bottom voltage for the pulse to see if I can reproduce the failure to set the flipflop. If I can, I have a way to test various solutions for correct operation. 

Without the correct diode and transistor models, I won't get the same results as I am observing but it let me explore variations in the pulse voltage dip and the pulse duration. I didn't find much sensitivity to a shorter pulse; it worked down to a 3ns duration and failed at 1ns. 

It was more sensitive to the bottom voltage of the pulse. I could get it to fail at 1.9V and work at 1.8V or lower. These aren't accurate since the semiconductors aren't accurately simulated. 

Another idea I explored is that cumulative capacitance is slowing the fall of the signal so that the duration is what limits the bottom level reached. This can be capacitance on my PCB, in the cable and in the 74HC03 chip, in addition to the backplane and receiving circuitry of the 5804619 card. I bumped the capacitor up and watched the signal closely to see whether I could reproduce the shape. Higher capacitance actually made it less sensitive. 

I then dug through my documentation for IBM SLT and found some parameters that let me refine the models for the diodes and transistors in the circuit. The new circuit with the models is:

This is modeling the shape of the pulse I am generating with my board. I found that it would fail to switch at 0.9V but switch at 0.8V or lower, much closer to the failure point I was seeing on my scope. 

dark blue is the input pulse

Even with the pulse duration extended by another 50 nanoseconds, the flip flop will not turn on when the pulse only dips to 0.85V. It is much more sensitive to the low voltage than it is to the duration of the pulse since it is edge triggered. 

I then dug into the spec sheet for the 74HC03 chip that generates the pulse and see that it is current limited compared to the demands of the flip flop edge detector. By varying the series resistance of a voltage source, I recreated the observed pulse shape with about 1K of resistance, but the flip flop needs about four times that current to flip. Interpolating the spec sheet to the 3.3V VCC I am using gets me to about 3ma of sink current, which is close to the effect of the 1K series resistance in the model. 

HAVE TO FIND NEW CHIP TO DRIVE THE SENSE OUTPUT PULSES

The simulation suggests that I need about 10-12ma of sink current to reliably flip the register on. Initially I found that a 74LVC1G138 chip provides a single 2 input NAND gate with open collector and can sink 16ma on a low output with a max of 0.4V which would be excellent if I had designed with that originally. It would require a new PCB to implement, adding more than a week of delay.

The best fit would be a chip that fits the same footprint and pinout, but sinks 12ma and operates with 3.3V VCC. The 74LCX38 chip is exactly what I want. It has the same pinout as the 74HC03, operates at 3.3V VCC, and can sink up to 24ma with a low output. It comes in an SOIC-14 narrow package that is compatible enough to solder onto my board as it is.

Now the challenge - buying the SOIC-14 version is going to be difficult. Through Digikey, I can only buy batches of chips from a marketplace dealer - Rochester.  Mouser does not carry the SOIC-14 version at all. Rochester will not sell less than $250 at a time - even though the chips are less than a dollar each. The manufacturer, OnSemi, points only at Rochester as a distributor stocking any of them. 

Of course, Amazon and eBay offer a number of vendors in China who promise they will send me the chips. In my experience, almost every vendor from China is selling fake chips - sometimes they are just marked with the part number but don't work. In other cases, they take a similar chip like the 74HC03, bleach off the identifier and remark it as the chip I want. The chip inside still won't deliver more than 3ma, so that would be a waste of money. 

Based on this, I might be forced into the PCB redesign where I have several options for chips I can buy. I guess if I can verify the design works through some Rube Goldberg adaption right now, I could finish testing on the 1130 and then order the new PCB and new chips. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 2

WATCHING SIGNALS FROM THE 1130 TO THE BOARD

My first check was to watch the +StorageRead, +StorageWrite and +StorageUse signals as well as -BBit0 where I could verify that the LOAD mode of the rotary mode switch was delivering the intended bit value. 

I was missing one of the key signals, +StorageWrite,  from where I expected it to arrive. However I did see the -BBit0 signal do the right thing based on the console entry switch settings during a LOAD. 

The next test watched both a -Bbitx and a -Sensebitx line to verify their pullup to +3V when not activated. These were pulled up to 3V on the bit lines I checked.

PLUGGED IN MY BOARD, WHICH DID NOT WORK CORRECTLY

One of the symptoms was that the 1130 recorded a word with bit 10 on any time I did a DISPLAY, which flagged a parity error since my board was outputting the parity check bits based on whatever was coming out of the memory chip. These would always be correct which meant that the 1130 was detecting differently than I was outputting. 

I still had the missing +StorageWrite signal issue to contend with. I decided to test continuity of all the signals from the source gates in the CPU out to my board - all 16 -BBitx, all 16 -Sensebitx, the two parity check -Sense bits, and the three input control signals +StorageRead, +StorageWrite and +StorageUse.

CONTINUITY CHECKS OF THE SIGNALS ARRIVING ON CABLES T1, T3 and T4

The Automated Logic Diagrams (ALD) are the source I used to document the cable pins associated with each signal to the memory gate B-C1. I found discrepancies from what I expected! 

The +StorageWrite signal was only detected on cable T3 at pin J1 A11 which I had listed as a duplicate of the signal on H1 D11. When I tested the continuity between those two pins while everything was plugged into the memory compartment, they were tied together. 

However, the connection between the two could have been implemented in one of three places - the compartment holding the source gate could send its output to both pins, the cable itself would have tied the two wires together, or the memory compartment could have tied the pins together on the SLT board where the cable plugs in. 

With the cable disconnected from the destination SLT board in the memory compartment, the pins were not tied together, thus the connection was done on the memory compartment SLT board we are replacing. I chose the wrong pin of the pair that are connected in the memory compartment. 

In an ALD, the gate producing a signal has a list at the bottom of the page of every pin where the signal is connected off this ALD page. For the +StorageWrite signal, the gate producing it is AY on page MC101. The list of off page destinations was:

This only shows connections from compartment 01B-B1 where gate AY is situated to other pins on 01B-B1, not to the memory compartment. However, you need to understand that the locations in the top row of any compartment are the T1, T2, T3 and T4 cables that connect to other compartments. Looking at the cable drawing below we can see that the last two pins on the list are part of cable T3 that runs from 01B-B1 to 01B-C1 (our memory compartment. 

Thus the signal from gate AY in MC101 goes to pin H1 E11 of the memory compartment through cable T3. There it is also tied to pin J1 A11 but only on the SLT board in compartment 01B-C1 which we are replacing. I chose the wrong pin to route on my PCB. 

In addition to the control signal, which was a major error that blocked correct operation of my board for any memory access, there were five more signals where a pair of pins were tied together in the memory compartment yet I picked the wrong pin of each pair for my PCB. These are:

• -BBit0 which I assumed was B1 A09 but instead was only routed to A1 E09 on the cable
• -BBit10 which I picked from L1 A09 but was wired only to K1 E09 on the cable
• -Sense Bit 3 which I picked as B1 D11 but was wired to A1 E11 on the cable
• -Sense Bit 7 which I picked as C1 D11 but was wired to C1 A11 on the cable
• -Sense Bit 13 which I picked as L1 D11 but was wired to K1 E11 on the cable

I can tack a wire on the back of my PCB to hook the pairs of pins together as they are tied on the memory compartment SLT board, which will resolve the issues. In my defense, I saw the signal duplicated on the cable and picked the pin that fit the pattern of the others, but that was the wrong choice electrically.

You can see above how the -BBit0 and -Sense Amp Bit 3 pins I chose are in line with the others and fall into a nice pattern, while the first two instances at the top seem out of place. 

When I get back to the workshop, I will rework the back of my PCB to tie together the six pairs of pins where I chose wrongly - every single duplicate I found by the way. Then I will test again. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 1

IT IS TIME TO HOOK THIS INTO THE 1130 AND TEST THERE

The three ribbon cables T1, T3 and T4 were disconnected from the gate B, compartment C1 backplane which houses the original core memory. These were inserted onto the connectors on my PCB. 

The red and black wires were connected onto the terminal strip TB2 just below gate B compartment C1 to provide the +12V power for my board. 

With that done, it was be time to power up the 1130 and check out the new memory.

TESTING ACCESS TO SOME WORDS USING THE LOAD FUNCTION

The IBM 1130 rotary mode control has a LOAD position, which uses the 16 console entry switches (CES) to input data and address values. I first set up an address on the CES then push the Load IAR button. This sets the memory address (SAR) to the chosen location. I change the CES to the data value I want to write into the chosen memory location and push the Start button on the console. This stores the value into the chosen memory location.

I put values into unique addresses using this method, then turn the rotary mode control to DISPLAY. In this mode, it reads the data in memory rather than writing it. First set up the chosen address on the CES and push Load IAR to select it. Next push the Start button to see the contents of that location display on the Storage Buffer Register (SBR) line of lights on the console.

RESULTS OF FIRST TESTS

When I attempted a DISPLAY the results were all zeroes with bad parity. I pulled out the oscilloscope to watch signals to see what is occurring. The line that I expected to see the +Storage Read signal appear was not changing. 

I will go home, review all the ALDs I have to ensure that I picked correct pins on the cables, then track down the exact issues tomorrow. I did verify that there were good voltages - +12V from the 1130 and +3.3V from the voltage regulator module - thus my board should be interacting. 

side project - IBM 3278 terminal restoration - planning for keyboard substitution

TERMINAL IS MISSING ITS ORIGINAL KEYBOARD

The 3278 terminals used the IBM beam spring type keyboards (type B), the most prized by keyboard afficionados for its feel. Thus keyboard pirates will find listings for devices like the 3278 and use only the keyboard. More often, recyclers or sellers of old gear will separate the keyboard as they can get 1-2 thousand US dollars for the keyboard itself. This leaves essentially useless terminals since the supply of keyboards has been hoovered up. 

The type B keyboard on the 3278 delivers a scan code in parallel on its interface for each key depression. These codes are associated with the position of the key-stem on the keyboard and therefore with the character printed on the keycap. 

The successor terminals like the 3178 made use of the 'type F' keyboard from IBM which is second best to the beam spring, but still desirable. Fortunately, not absurdly desirable and thus these can be found either together with their terminals or even separately for much more reasonable prices. 

The type F keyboard delivers a serial scan code, much like the later keyboards such as PS2, but the codes assigned to key-stems (and keycap characters) are different on most keys. It is feasible to read the scan code from a type M keyboard and translate that to a 3278 keyboard scan code, so that when the keycap with the character A is pressed, in the same key-stem position, the key code seen by the 3278 terminal will be the one that would have been sent by the beam spring keyboard. 

COMPLICATIONS TO DEAL WITH IN THE KEYBOARD SUBSTITUTION

The interface has wires for the seven bit scan code, power (+5, +8.5, -5, ground), power-on-reset, data available, make/break, keyboard ack, clicker, and four keyboard identifier bits. The identifier bits indicate the type of 3278 keyboard that was connected to the terminal. These include 75 and 87 key versions with different layouts. 

Many of the keys on the keyboard are called 'typeamatic', an IBM term that means if you hold the keycap down it will repeatedly emit that character, for example the space bar or a letter. Some are not. 

Some keys on the type B issue a different scan code for make (when it is pressed down) and break (when it is released) while most only issue one scan code. The type F indicates whether a keypress or a key release has occurred but we see both events. For the keys that don't have two scan codes on the type B, I can send only the make type scan code and drop the release. For those that will receive two scan codes on type B, I can map based on whether it was a make or break key action. 

There is an ALT button which changes the scan code issued for a key-stem. This only happens for the non-typeamatic keycaps; use of the Alt key involves emitting an Alt make code, the other key's scan code when it is subsequently pressed, and then the Alt break code when the Alt key is released - three scan codes emitted. 

The bottom right keycap (Enter key) is typeamatic on the type F but only emits one time no matter how long it is held down on the type B. I can resolve this by blocking repeated Enter scan code until a new character's scan code arrives from the type F. Since there is no Alt character assigned to this keystem, the fact that it is typeamatic and won't send the Alt make - Enter - Alt break sequence doesn't matter. 

The type F is a serial interface with one protocol, while the type B uses a parallel interface with a different protocol. I will need the two connector types and a microprocessor to handle the protocols on each connection, as well as handling the scan code mapping and other special handling mentioned above. 

Side project - IBM 3278 terminal restoration - looking into the high voltage power supply

REMOVED THE HV POWER SUPPLY AND OPENED IT UP TO INSPECT

The supply sits below the CRT inside the terminal. A connector brings 44VDC and a logic signal that disables the high voltage until the terminal logic is initialized and working properly. It also carries 400VDC to an accelerating electrode and a similar voltage to the focus electrode inside the CRT. A separate wire with a cap is plugged onto the side of the CRT to energize it with 18,000VDC. 

The supply consists of a small printed circuit board attached to a metal heat sink. The connector mentioned above, from the terminal, plugs into this board. Another connector has wires that go inside the metal box under the heat sink. 

Inside the metal box, I saw that everything was potted - sealed with a material that hides the parts underneath and keeps them from shifting about at all. This is helpful with very high voltages as parts that might shift due to handling of the terminal could come close enough to arc to other parts. The potting keeps all parts at their design distances. 

Unfortunately, the potting makes it very difficult to inspect, test or repair what is inside. A quick check with an ohmmeter shows infinite resistance between the anode cap and ground. I suspect some part has failed inside the potting resulting in a total lack of the 18KV power. 

THIS DOES NOT USE A FLYBACK TRANSFORMER FOR HIGH VOLTAGE

Most television sets make use of a flyback transformer to generate the high voltage for the CRT. The horizontal oscillator sweeps the beam across the tube, then at the right end of the line, the flyback transformer produces a powerful pulse to make the beam race back to the left extremely fast. This transformer also produces the anode voltage for the tube. If the horizontal oscillator is not running, there is no high voltage in this sort of design.

The 3278 terminal does have a horizontal oscillator which sweeps the beam across the tube, but it is not used to generate the anode voltage. Instead, as long as the 44VDC supply is present and the disable/enable logic signal allows the HV power supply to work, it will produce 400VDC and 18,000 VDC. It generates AC with an oscillator in the power supply, to drive transformers that step up to the target voltage. 

POTENTIAL SOLUTION FOR THE LACK OF 18KV POWER

It seems logical that the presence of 400V shows that the oscillator and driving circuits are working in the supply. It seems wasteful to create a second oscillator to drive the 18K stepup, thus it should be present since we have 400V coming from the supply.

This suggests to me that we have an open winding in the transformer or an open circuit in some voltage doubler components, but those are all inside the potting. If I can't fix that, I could install a replacement supply of 18KV. 

I did some quick checking and found availability of supplies that take 115VAC input and produce 18KVDC output, which would probably cost me about $100 or so to buy. I would add a method of disabling this driven by the disable/enable logic signal that does to the IBM HV power supply, thus my 18KV will only be delivered when the terminal is initialized. 

Before I commit to this, I should look at the outputs of the other circuitry in the terminal. If it is not producing scans and video output, the restoration might become unattractive. If I can see horizontal and vertical scanning plus a varying stream that would modulate the beam, then I could be more comfortable moving forward with the new power supply.

I will begin to plan the keyboard translator that will allow me to communicate with the terminal in spite of the fact that I don't have the 3278 keyboard - it was poached by keyboard pirates long ago. 

Success with the bench testing of the 1130 MRAM memory board finally

FINDING ROOT CAUSES

I have been plagued with erratic results, non-repeatability and other challenges in what should have been a straightforward verification of the correct operation of the memory replacement board. I began to suspect that the bench testing apparatus was causing these issues, not the board or its components. 

The Arduino had 16 data outputs and 13 address outputs that had to be connected to my board, in addition to the control signals that drive the read and write operations. For each of those lines, there was a male pin on my board and a female socket on the Arduino, which I connected with a M-M jumper plus a F-F jumper to change the gender. That means 3 connections for each of the 29 lines, none of them mechanically secure. 

I also used alligator clip jumpers and pin jumpers to connect grounds between the Arduino and my board as well as connecting to a breadboard where I had the pullup resistors for the sense output lines of my board. The Arduino ground is just a few pin sockets. I believe that slight vibrations were causing noise or corrupting signals as this setup was just too fragile to trust the results. 

FIXING THE ISSUES

The writing program was changed to perform a read back of the address right after the write cycle. I pulled all the address lines off as I already know it was correctly addressing memory, thus all further testing was done just with location 0. That eliminated 13 signals and 39 connections. 

I moved the 16 data connections from the Arduino to the breadboard and set it up so that a slide switch would set the data to 0 or 1. The Arduino was only emitting the Storage Write and the Storage Read control signals now. 

TESTING RESULTS

I was able to verify that all 16 sense output lines were producing the data that I had just written, reliably. I checked the checksum output lines as well and verified that they were giving me the pulses needed to achieve odd parity on each 8 bit halfword coming from memory. 

I am now satisfied that this works properly, so that I can attach it to the 1130 system and test it there. 

The board above with its bodge wires and the outboard voltage regulator module needs conformal spray and then a metal can placed over the MRAM chip to reduce stray magnetic fields that might change the data stored on the chip. 

side project - restoration of IBM 3278 terminal - some debugging

ALL LOW VOLTAGE SUPPLY LEVELS ARE GOOD

The LV power supply produces a range of voltages for the digital logic, memory chips, analog logic and to power the High Voltage (HV) supply. I verified the presence of +5, -5, +8.5, +8, -12, -44 and +44 VDC as well as the 6.3VAC for the display tube filament. 

SOME OF THE HIGH VOLTAGE IS WORKING BUT NOT ALL

The HV power supply produces voltages such as 400V for accelerating the electron stream towards the front of the screen - those are present. However, the tube needs a really high voltage to produce a nice bright image on the phosphors. The supply is NOT producing the 18,000V which is why the tube isn't showing anything. 

NO SCHEMATICS THUS I WILL HAVE TO REVERSE ENGINEER IT

If I figure out enough of the circuit to figure out why it is not generating the very high voltage, I might be able to fix it. That assumes that it is a repairable part or that I can find a compatible 18KV supply from an oscilloscope or similar CRT device. 

side project - restoration of IBM 3278 terminal - inspect, mechanical fixes, first power on

REMOVED COVERS AND LOOKED OVER THE TERMINAL

The covers were set aside and I could then see everything inside. The terminal looked complete and nothing was obviously damage inside. 

MECHANICAL TWEAKING OF FRAME AND HOLDERS

The covers and the mounts inside had been twisted and loosened, although based on the pictures posted from eBay this may have happened before shipment. I straightened them as well as I could. 

More work on bench testing for the 1130 MRAM core memory board

IMPLEMENTED BACKFEED PROTECTION CIRCUIT

I put a through hole IRF540N MOSFET on the prototyping tool breadboard, isolating the ground of my PCB until a voltage divider from the +12V bench supply feed is active. This low side isolation ensures no back-feed current will flow from the Arduino or any other input to the board unless we have our power turned on. 

REPLACED ONE OF THE BUFFER CHIPS ON THE BOARD

I had lifted a 74LV240 inverting buffer chip from the PCB while investigating the observed steady 1 voltage on the bit 14 net that had been producing a pulse on sense bit 14 for any and all addresses. I put a spare chip on the board so that I can write zero and one values to verify the memory chip is working.

I RESUMED BENCH TESTING BUT STILL HAVE POWER ANOMALIES

I checked to see if there was any back-feed voltage on the PCB with the Arduino active while I was not feeding voltage from the bench supply to the board. I used an ammeter on the ground line that passes through the MOSFET. After this was validated, with no current until I triggered the MOSFET, I thought I was ready for function testing. 

However, strange things are still happening. When I power the board from the bench supply, there is no indicated amps or watts being consumed when the MOSFET is connected. When I disconnected the MOSFET, I saw about 7ma of draw on the supply! At first I thought it might be my pullup resistors for the scope probes when monitoring the sense output pulses, but with those disconnected I still had 7ma flowing somewhere. 

I pulled the USB connection for the Arduino Due and my current disappeared! The Arduino is pulling current which is very odd since I have nothing but output pins defined on the Arduino. It isn't backfeed - it occurs when the Arduino is powered, not when it is getting power from my board. In fact, my board's outputs are open collector, with pullup done on the prototype breadboard (disconnected) not by my PCB components, so there is no voltage that should flow from my board to the Arduino configured in output mode - at least I don't expect there is any. 

I am going to disconnect groups of pins from the Arduino and monitor the current draw while my MOSFET is isolating my circuitry, until I get more of a clue to where this power consumption is going. The 12V from the bench supply flows through a regulator module to create 3.3V first, which means the draw is larger on the 3.3V rail than what I see on the bench supply. 

IMPROVED BENCH SETUP TO MONITOR PINS OF SMD CHIPS ON MY BOARD

I found it cumbersome to tack tiny wires on the pins of various chips in order to observe the signals during read and writes, so I pulled out my PCBite and put my board on that. This has probes with teeny pins suitable for measuring a surface mount chip pin, held in place with magnets onto the base plate. With my board anchored and the four probes set up, I could watch different pins as I study the function of the board in more detail. 

Using LT SPICE to study back feed voltages from digital inputs when power supply not operating

BACK FEED ISSUES I WANT TO AVOID

Digital abstractions for logic gates and other chips mask the analog reality of those devices, where the components inside have complicated behaviors that can produce results in the real world that don't exist under the abstraction.

For example, a NAND gate with two inputs and an output can feed power into its own chip and all the others on a board if the input to the gate is powered but the board is otherwise not powered. I would observe the board producing outputs but I hadn't turned on the bench power supply yet. 

This occurs because the input circuits of the NAND gate has protective diodes on the input - one of which will pass the power from the input to the VCC pin in the unpowered gate, powered input case I mentioned. That input pin is then providing all the current demanded by the chips on the board. The chip can easily be damaged because of that. There is even the chance that the power demands of the input can be more than the driving device (an Arduino Due in my case) can source, damaging the Arduino.

I set up a MOSFET to interrupt the low side (ground) of the board if the bench power supply isn't delivering voltage to the board. With the ground of the board isolated from the ground of the Arduino Due or other source to the input pins, no current will flow. 

The MOSFET is a complex device in reality, as is the voltage regulator providing the 3.3V from the 12V of the bench supply. Therefore I wanted to examine the real world behavior of these to see whether there is any back feed voltage and current pulled from the 

RAN LTSPICE SIMULATION OF THE BACK-FEED PROTECTION

I set up a schematic with the MOSFET circuit I will use for isolating the low side (ground) of my PCB. A diode representing an input protective diode on a logic gate as connected to a 3V voltage source to represent the source of back-feed. I then modeled the current flowing through my PCB circuits (represented by a simple load resistor in this model) while I alternated the control signal between 0V and 12V. It worked exactly as I expected, ensuring virtually no current flowed from the powered input pins of my PCB until the +12V was present. The simulation showed nanoamps of current flow due to the non-ideal nature of the MOSFET, but that is negligible.

I then set up a schematic with the LDL1117 voltage regulator I intend to use on future boards to replace the outboard voltage regulator module, dropping the +12V (or slightly higher) down to 3.3V for the chips on the board. I modeled what happened with the input pins of the board driven by 3 or 3.5V while the regulator chip was unpowered. I saw a slight voltage and only microamps flowing out of the regulators power input. This is insufficient to energize my MOSFET to connect the board ground to the grounds of the rest of the setup. 

Side project - restoration of IBM 3278 terminal - shipment arrives

QUICK LOOK AT THE OUTSIDE OF THE PACKAGE

It was delivered today. The box is a bit beat up but intact. More importantly, I don't hear any tinkling of broken glass which is a good omen for the condition once I open it. 

BROUGHT TO WORKSHOP FOR FUTURE WORK

I will set it up next to its 3178 and 3179 brethren on a table in the shop. I have a 3174 controller and other equipment which will allow these to be connected to my P390 system allowing me to interact with IBM mainframe software via real terminals. 

First thing though is to unpack the box and assess the condition. I have guests visiting for a couple of days but when they have left I can get to it. 

Bench testing of the 1130 MRAM core memory board still not successful

MODIFIED THE CONTROL SIGNAL DESIGN OF THE BOARD

I had noticed that the data bits being passed through the buffer from the B register did not settle rapidly due to capacitance in the circuits, both on my board and the bench test setup. With a pulse width of 80 nanoseconds for both buffer enable and write, I was concerned that the data was not properly set up on the MRAM chip pins by the time the chip locked the data in for the write. 

The chip enable signal ~E is unchanged. It is asserted low when we have both +12V supply from the 1130 computing system and the Storage Use signal from the 1130 is asserted. 

The chip write signal ~W is unchanged. It is asserted low when we have Storage Write asserted and the write timer produces its 80 nanosecond pulse. 

The chip output enable signal ~G that drives the data output pins is asserted low when Storage Write is low.  During the read part of a memory cycle, Storage Read is asserted high and Storage Write is asserted low. 

The buffer enable control signal ~IO is asserted low when Storage Write is asserted high. 

The sense output pulses occur when the read timer pulse is active, some time after Storage Read is asserted. This is unchanged. 

I had to cut traces and apply bodge wires to implement the new scheme with the existing board. Due to traces passing underneath chip U14 where the control signals are generated, I had to temporarily remove the chip, modify the board and then solder the chip back down. 

Traces cut underneath chip U14

Trace cut to ~W pin on MRAM chip

Bodge wiring added

REDID THE WRITING PROGRAM AND THEN OBSERVED THE READING

The writing program was changed to loop through all of memory, storing a data value equal to the storage address in each word. The reading program now takes input over the serial monitor with an address to read, thus allowing me to read any desired address while observing the output pins. 

I could check the various addresses that are powers of two, verifying that only the sense output bit that matched the power of two from the address would be 1, with all others producing no pulse. Some random addresses that were not a power of two could be read to check the appropriateness of the sense output pulses. 

Lastly, I scoped the two parity output bits to see that the correct bit was output for each of the selected addresses. The board produces a parity bit to provide odd parity for each halfword (eight of the sixteen data bits), so that the number of pulses being produced in that halfword is an odd number. 

When the output word is zero, for instance, both parity bits should pulse to provide correct parity. With the values I am reading, there is only one bit that is 1 so the halfword that contains the bit should have no pulse on its parity line while the other needs to pulse. 

TESTING ON THE BENCH AFTER THESE CHANGES

I ran the new memory write program on the Arduino to configure the MRAM memory. I then started checking with the new memory read program and the oscilloscope. All bits came back as 0 for any address except for sense bit 14 which always returned a 1 pulse. Checking the static voltages showed that with the ~G signal asserted to output the memory contents, the net for bit 14 was at logic 1 level. 

It wasn't clear whether the MRAM chip was driving the 1 or that something else was wrong. If the 74LV240 inverting buffer chip was malfunctioning, it might be forcing output in spite of its control signal ~IO being at logic high (disabled) so that it should be in high impedance mode 

I then did a static check on ~IO to confirm that it was at logic high. I checked both of the 74LV240 chips, one for each eight bits of the word, to see if the results were different on the other half of the word. 

I was able to successfully load various patterns into bits 0 to 7 of some memory locations, thus confirming that the basics of my design work. However, bit 14 continues to show a high value regardless of what data is written there and for any memory address. 

One other issue I detected was that the parity generation process is now producing a check bit regardless of the number of 1 bits in the half word. 

As a final test of this possibility, I removed the 74LV240 chips from the board and did another set of read tests. There should only be outputs driven by the MRAM chip on the nets, thus sense bits should all reflect what the chip is emitting and nothing else. Bit 14 remains high while the others are not - that could be because I have written a 1 into all the addresses due to a defect in the removed chip, or it could represent a failure in the MRAM chip. 

POWER BACKFEED DIFFERENT FROM THE ORIGINAL LAPTOP CHARGER CASE

I noticed that the sense output pulses were being produced by the board but the power supply to the board was turned off! This highlighted that my bench testing setup is backfeeding the board through the protection diodes in the chips. That is not good. The current flow from a backfeed can damage the chips on the PCB. 

NEED TO RETHINK THE TEST BENCH SETUP - PLUS SWAP ALL THE CHIPS AGAIN

The setup I had been using has a prototyping breadboard setup that I used to implement the pull up resistors for the sense output lines. It had a main power supply to the PCB, with a bench supply delivering 12V that is then regulated down to 3.3V for the chips on the board. Finally, there is an Arduino Due that is being powered through the USB cable from my laptop. 

The Arduino is producing 3.3V logic high signals which I suspect is the cause of the backfeed of power. The prototyping setup has 3.3V but that is connected to open collector output chips on thus board thus not causing backfeed. 

There is one final vulnerability in my design. I  drop the 12V power coming from the bench supply (and eventually from the 1130 CPU) down and apply it as a logic input to produce the memory chip enable signal. This is a potential backfeed through the input of the logic gate if the 3.3V regulator output is not present or lower than the voltage divider result. 

I have ordered a full set up chips for the board in order to replace anything that was damaged during the testing regimen. This will take about a week to arrive, after which I will install them and begin testing with a new backfeed safe setup. 

BACKFEED PROTECTION WORKED OUT

To avoid backfeed, I can't have any voltage on a input that is higher than the VCC supply voltage and those voltages to inputs must absolutely not be delivered unless the board's power supply is active. 

I could power the Arduino through a MOSFET so that when my VCC is off, the Arduino is off and not supplying any power to input pins. That means it must not take power from the USB port, only through my MOSFET supply; generally that means a modification to the Arduino board. 

There remains the production use case where the IBM 1130 +3V power rail is active but the +12V is not active, either during power-up and power-down or due to loss of the other 1130 power rails. This will be pulling the inputs up to +3V and backfeeding power to my board. I need a solution to this, ideally one that does not require 29 sets of parts for the protection. 

The solution is to use a MOSFET to isolate the ground to my PCB unless there is the +12V supply available. When no +12V exists, the board is isolated from ground and this eliminates any power flowing into the board from the B reg or SAR inputs. It also blocks the +12V resistor divider from dropping the 12V but since the ground is isolated this doesn't inject power into the gates. 

This solution allows me to use the USB power to the Arduino without any modifications, since my board is isolated from the Arduino when VCC is not delivered to my board because my bench supply is not delivering the +12V to the regulator and board.