MODIFIED THE CONTROL SIGNAL DESIGN OF THE BOARD
I had noticed that the data bits being passed through the buffer from the B register did not settle rapidly due to capacitance in the circuits, both on my board and the bench test setup. With a pulse width of 80 nanoseconds for both buffer enable and write, I was concerned that the data was not properly set up on the MRAM chip pins by the time the chip locked the data in for the write.
The chip enable signal ~E is unchanged. It is asserted low when we have both +12V supply from the 1130 computing system and the Storage Use signal from the 1130 is asserted.
The chip write signal ~W is unchanged. It is asserted low when we have Storage Write asserted and the write timer produces its 80 nanosecond pulse.
The chip output enable signal ~G that drives the data output pins is asserted low when Storage Write is low. During the read part of a memory cycle, Storage Read is asserted high and Storage Write is asserted low.
The buffer enable control signal ~IO is asserted low when Storage Write is asserted high.
The sense output pulses occur when the read timer pulse is active, some time after Storage Read is asserted. This is unchanged.
I had to cut traces and apply bodge wires to implement the new scheme with the existing board. Due to traces passing underneath chip U14 where the control signals are generated, I had to temporarily remove the chip, modify the board and then solder the chip back down.
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Traces cut underneath chip U14 |
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Trace cut to ~W pin on MRAM chip |
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Bodge wiring added |
REDID THE WRITING PROGRAM AND THEN OBSERVED THE READING
The writing program was changed to loop through all of memory, storing a data value equal to the storage address in each word. The reading program now takes input over the serial monitor with an address to read, thus allowing me to read any desired address while observing the output pins.
I could check the various addresses that are powers of two, verifying that only the sense output bit that matched the power of two from the address would be 1, with all others producing no pulse. Some random addresses that were not a power of two could be read to check the appropriateness of the sense output pulses.
Lastly, I scoped the two parity output bits to see that the correct bit was output for each of the selected addresses. The board produces a parity bit to provide odd parity for each halfword (eight of the sixteen data bits), so that the number of pulses being produced in that halfword is an odd number.
When the output word is zero, for instance, both parity bits should pulse to provide correct parity. With the values I am reading, there is only one bit that is 1 so the halfword that contains the bit should have no pulse on its parity line while the other needs to pulse.
TESTING ON THE BENCH AFTER THESE CHANGES
I ran the new memory write program on the Arduino to configure the MRAM memory. I then started checking with the new memory read program and the oscilloscope. All bits came back as 0 for any address except for sense bit 14 which always returned a 1 pulse. Checking the static voltages showed that with the ~G signal asserted to output the memory contents, the net for bit 14 was at logic 1 level.
It wasn't clear whether the MRAM chip was driving the 1 or that something else was wrong. If the 74LV240 inverting buffer chip was malfunctioning, it might be forcing output in spite of its control signal ~IO being at logic high (disabled) so that it should be in high impedance mode
I then did a static check on ~IO to confirm that it was at logic high. I checked both of the 74LV240 chips, one for each eight bits of the word, to see if the results were different on the other half of the word.
I was able to successfully load various patterns into bits 0 to 7 of some memory locations, thus confirming that the basics of my design work. However, bit 14 continues to show a high value regardless of what data is written there and for any memory address.
One other issue I detected was that the parity generation process is now producing a check bit regardless of the number of 1 bits in the half word.
As a final test of this possibility, I removed the 74LV240 chips from the board and did another set of read tests. There should only be outputs driven by the MRAM chip on the nets, thus sense bits should all reflect what the chip is emitting and nothing else. Bit 14 remains high while the others are not - that could be because I have written a 1 into all the addresses due to a defect in the removed chip, or it could represent a failure in the MRAM chip.
POWER BACKFEED DIFFERENT FROM THE ORIGINAL LAPTOP CHARGER CASE
I noticed that the sense output pulses were being produced by the board but the power supply to the board was turned off! This highlighted that my bench testing setup is backfeeding the board through the protection diodes in the chips. That is not good. The current flow from a backfeed can damage the chips on the PCB.
NEED TO RETHINK THE TEST BENCH SETUP - PLUS SWAP ALL THE CHIPS AGAIN
The setup I had been using has a prototyping breadboard setup that I used to implement the pull up resistors for the sense output lines. It had a main power supply to the PCB, with a bench supply delivering 12V that is then regulated down to 3.3V for the chips on the board. Finally, there is an Arduino Due that is being powered through the USB cable from my laptop.
The Arduino is producing 3.3V logic high signals which I suspect is the cause of the backfeed of power. The prototyping setup has 3.3V but that is connected to open collector output chips on thus board thus not causing backfeed.
There is one final vulnerability in my design. I drop the 12V power coming from the bench supply (and eventually from the 1130 CPU) down and apply it as a logic input to produce the memory chip enable signal. This is a potential backfeed through the input of the logic gate if the 3.3V regulator output is not present or lower than the voltage divider result.
I have ordered a full set up chips for the board in order to replace anything that was damaged during the testing regimen. This will take about a week to arrive, after which I will install them and begin testing with a new backfeed safe setup.
BACKFEED PROTECTION WORKED OUT
To avoid backfeed, I can't have any voltage on a input that is higher than the VCC supply voltage and those voltages to inputs must absolutely not be delivered unless the board's power supply is active.
I could power the Arduino through a MOSFET so that when my VCC is off, the Arduino is off and not supplying any power to input pins. That means it must not take power from the USB port, only through my MOSFET supply; generally that means a modification to the Arduino board.
There remains the production use case where the IBM 1130 +3V power rail is active but the +12V is not active, either during power-up and power-down or due to loss of the other 1130 power rails. This will be pulling the inputs up to +3V and backfeeding power to my board. I need a solution to this, ideally one that does not require 29 sets of parts for the protection.
The solution is to use a MOSFET to isolate the ground to my PCB unless there is the +12V supply available. When no +12V exists, the board is isolated from ground and this eliminates any power flowing into the board from the B reg or SAR inputs. It also blocks the +12V resistor divider from dropping the 12V but since the ground is isolated this doesn't inject power into the gates.
This solution allows me to use the USB power to the Arduino without any modifications, since my board is isolated from the Arduino when VCC is not delivered to my board because my bench supply is not delivering the +12V to the regulator and board.