Wrapping up build and bench testing of the 1130 MRAM memory replacement board

DID A FULL TEST OF THE INPUTS, PARITY GENERATION AND OUTPUTS

Inserting a 1 on each bit position of the MRAM data lines produced a change in the associated parity output, just as it should. Each pad was touched to validate the behavior. I then tacked a wire on each of the MRAM data lines and injected a 1 or 0 into the B register (data inputs from the CPU). When I asserted the Storage Write line the value showed up for the duration of the 100 ns pulse that also triggers the MRAM write operation. 

When I tested each output I discovered to my chagrin that I had put AND gates in the output lines, which produced a positive going 100ns pulse for each 1 injected into the MRAM data pads. The CPU expects a negative going pulse, however. I ordered open collector NAND gates and will swap them into the board as soon as they arrive. 

MEMORY CHIP INSTALLED 

The MRAM chip is soldered into place as the last step, once all the circuitry that drives and supports it appears to be working properly. At this point the board is functionally complete, although I am still waiting on the proper value capacitors in surface mount packaging and for the NAND gates I just ordered. 

Above you can see the board with the temporary capacitors on the right and a wire tacked on to replace the 3.3V regulator that was going to be on the board. In the picture I had begun to install the SLT pins where the cable from the CPU will plug into the board. 

SLT PINS INSTALLED

The last set of pins will be installed on the board so that the SLT ribbon connectors T1, T3 and T4 between the 1130 and this board can be plugged in. That will complete assembly, after which testing must be done with the 1130 system.