More testing of the 1130 MRAM memory replacement board - part 2

HOOKED UP ARDUINO DUE TO SIMULATE THE CPU SIGNALS

An Arduino Due will develop the three input signals at the proper timing. I coded this up using the timers on the Due SAM chip, which are handled differently than the ATMEL chip timers in the other Arduino boards. I used the half speed clock timer1 running at 42MHz, then set up the compare register A in the timer to 38 and compare register C to 76. 

Starting the timer in wave generation gives us a 50% duty cycle square wave at 560 KHz or about 1.8 microseconds per cycle. It interrupts when hitting these register values, allowing us to flip digital pins 2 and 3 on and off to form Storage Read and Storage Write. Pin 4 is Storage Use. We run with pin 4 off for six seconds then flip it on for the duration. 

We can display several signals on an oscilloscope to verify that this circuitry drives E, G, W and the two buffer control signals at the intended times and only for memory cycles with Storage Use asserted. I had to tack on wires to drive the three control signals on my board, plus some wires to detect the output of E, G, W, sense pulse output and buffer enable. With four channels, I set one to Storage Read and monitored three at a time on the other channels. 

The timing for various actions on the board is show in the diagram below. As soon as we start the read part of the cycle, the chip does a read and leaves the data bits on its output pins (purple). The timing chain does a delay of 800 ns (green) and then emits an 80 ns pulse (turquoise). If the data bit from the MRAM read is a 1, the pulse is passed through as a sense bit. In the write cycle, we gate the B Bit signals to the MRAM chip during the entire write cycle. The write delay (red) takes 800 ns then a pulse is emitted (yellow). This is passed to the MRAM chip to command a write operation (orange). 

The chip enable signal E should turn on whenever we have +12V to the board and the Storage Use signal is asserted. Signal G to set the MRAM chip data lines to output mode should be turned on whenever we are in a read cycle and E is enabled. Signal W requests the MRAM chip to write the data on its data pins into the location configured by the address bits; this signal is turned on by the write control pulse from the timer chain during a write cycle. 

The buffer chips normally sit in high impedance mode, not driving any data on to the MRAM chip data lines. When we have the write control pulse during a write cycle, we activate the buffer to pass the data to the MRAM chip. We are activating the buffer at the same time that we start the write in the MRAM chip, so there is a bit of settling of the data values immediately but the memory chip only samples later in the write operation when the buffer outputs will be stable. 

The sense output pulses are generated by the read cycle timer chain with the pulse at 800 to 880 nanoseconds into the cycle, when the data from the memory location was read and became stable about 45 ns into the cycle. It is 'sampled' at 800-880 ns where we either have an 80 ns open collector pulldown to ground if the data bit value was 1 or we have the sense output staying pulled high. 

IMPROVED TIMING WITH CHANGE TO CAPACITORS

I substituted some different valued capacitors until I got the timing chains to behave closer to my target. The final 680 pf choice gave me just about perfect delay into the midst of the read and write cycles, while a 33 pf part reduced the pulse width down to 100 ns. That is close enough that I will lock in these values and move on. 

All the signals looked perfect. I carefully studied the MRAM chip control signals for gating the data out on the bidirectional pins, for requesting a write of data coming in on the bidirectional pins and for disabling the chip so it is insensitive to other signals. The signals that pass the incoming data through to the MRAM chip and initiate a write looked exactly as they should. Finally, the signals were right on time to create a pulse for any data bit whose value was 1, sending those out to the CPU. 

INPUT AND OUTPUT BUFFERS INSTALLED

The chips that take the data input from the CPU and connect it to the memory chip must leave the memory chip pins in high impedance except for when we are doing a write and it is the appropriate time to drive the data input signals onto the memory chip pins. They were all soldered onto the board and carefully checked for shorts/solder bridges. 

We validated the control signals in the prior test, but tomorrow I will double check that no signals are driven into the memory chip except when we intend to.

The chips that output a pulse on the sense lines should only drive a pulse (open collector gate pulled to ground for the pulse duration) when Storage Use is true and it is the proper time. Further it should only send a pulse when the bit retrieved from memory is a 1. I will test this tomorrow as well. 

The Arduino will continue to drive the control signals in place of the CPU. We will inject values as if the memory chip were installed, in order to test the output buffers. We will probe the inputs where the memory chip will be installed to verify that no 1 bits arrive except those we introduce to the input side of the input buffer chips. 

PARITY GENERATING XOR CASCADE INSTALLED

A group of chips will generate a parity bit P1 or P2 based on the eight bit values being output from the memory chip during a read. P1 and P2 also connect to the output buffers to the sense lines - these are to be checked tomorrow by inserting some ones on the empty memory chip pads and observing the sense line output.