Finished trace by trace and datasheet by datasheet examination; one issue arose that must be pondered

COMPLETED ALL THE DESK CHECKING

I very carefully examined all the data sheets and documented the pin assignments, footprints and logic rules for each chip used on the board. I then traced each signal on the PCB to ensure that it went exactly where it should and had the intended meaning. I submitted my final parts order and was preparing to send the design off to the PCB fab when I happened upon an unpleasant surprise. 

FOUND THAT STORAGE SELECT IS A PULSE NOT A STEADY SIGNAL

I happened to look at the ALD page that generates +Storage Select which I believed was steady state during a core access cycle. Instead, I saw that it is produced only during the T0, T4, X0 and X4 clock phases where it triggers a single shot to produce a pulse. After digging through many documents I finally found a chart showing the 100ns long pulses produced.

The logic page for the signal generation showed the circuit below.

The falling edge of any of those four clock pulses will trigger the single shot to generate a positive going 100 nanosecond pulse. A memory cycle on the 1130 is a sequence of eight clock steps T0 through T7. The first four are the read of the addressed word and the second four are the write-back (or update) of the word. Peripherals using cycle stealing (direct memory access in modern terminology) will instead do a memory cycle using clock steps X0 to X7 while the T clock idle. 

IMPLICATIONS OF THE PULSE

I combine +Storage Select with a sense signal showing +12V input is present, then combine that with +Storage Use to enable the MRAM chip. Further, that combination of 12V, +Storage Select and +Storage Use is combined with +Storage Read to enable the bidirectional pins on the MRAM to output the word contents. 

Because +Storage Select is only 100 ns, I will disable the chip before my read timer grabs the word contents from the bidirectional pins and outputs them to the CPU. Further, the chip will be disabled before my write timer gates the Storage Buffer Register (SBR) data bits to the memory chip bidirectional  pins and before I assert the signal to perform a write. 

RESOLUTION

While the CPU is actively running, executing instructions, the clock is advancing through the eight T or X clock steps. It is producing +Storage Read for 1.8 uS then +Storage Write for another 1.8 uS. It would be sufficient to use +Storage Use to enable the chip and +Storage Read and +Storage Write to trigger my timers. I could treat +Storage Select as a constant high signal. 

Now thinking about when the CPU clock is halted - a Wait instruction, the Stop button or other such conditions - The T and X clocks are both sitting idle. +Storage Write would still be active at the end of the prior memory cycle. The logic that generates +Storage Read and +Storage Write is shown below.

If any of T0, T1, T2, T3, X0, X1, X2 or X3 are active, the input on the left above will drive low which produces a logic high on +Storage Read and a logic low on +Storage Write. The clock stops at T7 and X7 when stopped/idle. Thus +Storage Write goes high at T4 of the prior memory access and stays that way until the clock starts again. 

My read timer triggers when +Storage Read goes high, which won't occur while the machine clock is stopped. My write timer triggers at the rising edge of +Storage Write, but the signal is steady high while we are stopped thus no triggering. 

Therefore, if I ignore +Storage Select and act as if it is logic high, the memory should still work properly. The detail of a memory access cycle below shows when events occur and how my design treats them.

1. The machine is running or Start was pushed so that it is ready to advance from T7 and X7 at the end of the prior cycle. 
2. If the +Storage Use is logic low, then we ignore any further signals for the cycle T0 to T7 (or X0-X7).  It is is logic high, we enable the MRAM chip with the E control signal.
3. An address is placed on the Storage Address Register (SAR) and +Storage Use is logic high to request a memory access cycle.
4. The machine moves to T0 or X0 clock step. +Storage Write goes low and +Storage Read goes high. 
5. The read timer begins an 800 ns delay.
6. The output enable signal G is set on the MRAM chip so that it will display the word contents on its bidirectional output pins
7. The chip completes a read of the SAR address in about 35 ns, while we are still in T0 or X0, then leaves the data value on the bidirectional pins.
8. The machine advances to clock step T1 or X1. The read timer is going to finish its 800 ns delay near the end of this clock step. The data from the addressed memory location remains on the bidirectional pins.
9. The read timer starts an 80-90 ns control signal which causes any bit of the word that was a 1 to emit a logic low output on the -Sense Bit x line for the duration of the control signal. Other than when we have the control signal and a 1 bit on the bidirectional pin, the =Sense Bit x line remains logic high. 
10. The CPU moves into clock step T2 or X2. The output on -Sense Bit x will finish early in this clock step. 
11. The CPU moves into clock step T3 or X3. 
12. The CPU moves into clock step T4 or X4. +Storage Read goes logic low, while +Storage Write goes logic high. The output enable signal G is deasserted and the bidirectional pins on the MRAM chip are in high impedance waiting to have data driven into them. The write control signal W is not asserted at this time.  
13. The leading edge of +Storage Write triggers the write timer to produce an 800 ns delay. 
14. The CPU moves into clock step T5 or X5. The write timer delay will go finish near the end of this clock step.
15. The write timer produces an 80-90 ns control signal that is connected to the write control pin W of the MRAM chip and also to the enable pins of the buffer that gates the SBR data bits onto the MRAM bidirectional pins. 
16. The MRAM chip performs a write in 35 nanoseconds using the data from the SBR at the address in the SAR. 
17. The CPU moves into clock step T6 or X6. The write control signal from the write timer will end early in this clock step. The buffer stops driving the SBR data onto the MRAM bidirectional pins. 
18. The CPU moves into clock step T7 or X7. 
19. If the machine needs to stop, it stays in T7 or X7. It will advance to T0/X0 to start another memory cycle if it is not stopped. 

Thus my fix is pretty simple. I will adjust the schematic and PCB design then send it off to be fabricated. 

APPENDIX ON WHEN THE CPU IS STOPPED OR RUNNING

When in Run mode, the machine advances immediately to the next memory cycle. When the Start button is pressed, it advances to T0 for the next memory cycle. When a peripheral device requests a cycle steal to transfer data. the clock advances to X0. 

The CPU stops based on the rotary mode control, either after a clock step, a memory cycle or a complete instruction execution which entails multiple memory accesses. The Stop button and other conditions can also cause the CPU to stop, including execution of a Wait instruction.