Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 3

RESOLVED THE PIN ASSIGNMENT MISTAKE ON MY PCB

I installed jumper wires on the six pairs of pins I had previously identified. In addition, I discovered three more pairs that have the same characteristics - -Sense Bit 17, +SAR Bit 3 and +SAR Bit 10. Those were also jumpered on the backside of my board. 

TESTING WITH LOAD AND DISLAY MODE

I still saw parity errors when doing a DISPLAY on any address, but when watching the signals I could tell that I was in fact writing the 1 or 0 value into memory and then generating a pulse on the sense output line when the bit stored was a 1. 

However, B register bit was NOT being set when that pulse occurred, s it should. There is a flipflop in the B register circuitry that will be set if there is a falling edge on its input - that comes from my circuitry. 

THE ISSUE IS THE PULLDOWN CURRENT FROM MY BOARD (OR DURATION)

The sense output bit is generated by a 74HC03 gate, a NAND with open collector output where the gate pulls the output to ground when activated. The pulse may  not be long enough, at about 100 nanosecond duration, since the IBM core memory circuitry produces that pulse with a duration more like 180 ns. It is the falling edge that causes the action, not the duration, so that shouldn't matter. If it does, I could adjust it by swapping the capacitor that determines the length of the pulse I produce. 

However, what is more objectionable is the low point of the pulse I am producing. It is not down to zero volts, instead reaching no lower than about .6 volts which is way above the SLT logic zero definition. Since my gate is conducting to ground, I expected it to get much closer to 0V. 

Looking at the spec sheet for the 74HC03, it does show that with a 4.5V VCC (we are at 3.3V) and a 4ma current sunk by the gate at logic low, the voltage is typically .33V, which is already too high for SLT. As with all issue with digital logic, one has to look below the abstraction at the real analog behavior to understand why it is not switching. 

There has to be enough current to reverse the conduction of a pair of transistors at the heart of the flip-flop. This will depend on the resistors and other contributors to resistance as well as the current sink capability of the driving transistor in my gate. The flipflop is shown as consisting of several circuit elements in this IBM diagram below:

In the IBM documentation, circuit segments are named with codes such as T20SC, the first letter indicating the speed of the circuit which is 30ns in this case. The two digits define a logic function, then the suffix letters indicate the variant with differences such as resistor values used. I don't have a full set of schematics for these circuit segments but can find some (or close family members) in schematics I do have for certain SLT cards. 

This section of a 5804628 card schematic has a section where the only variance is in the two AND blocks which are S03AJ instead of S03SQ. 

The schematic for the T20xx circuits is:

The S03xx circuit attaches to one of the outer transistor collectors above such as pad 4 or 11.  On this card it uses an S03AJ circuit but we are more interested in the S03SQ which better matches our B register card. 

I then looked through other cards with flip-flops until I found the S03SQ circuit schematic on a 5803794 card:

Connector 2 above is what connects to the T20AB circuit connections to set or reset the flipflop. Connector 3 above is what connects to the output of the flipflop which blocks a set or reset from passing through if the flipflop is already in that state. Connector 6 above is the gate signal that sensitizes this circuit - when it is at logic low, a falling edge on connector 1 above will send a pulse to the flipflop. 

My board has to send a falling edge that will pull the charge from 33 pF capacitor, thus pulling down the base of a transistor in the flipflop, through a diode, causing it to conduct and flip the state. To clarify the discussion a bit, we are looking at the signals to set the flipflop when my sense bit pulse has a falling edge. 

SIMULATION TO UNDERSTAND CORRECT AND FAILING OPERATION

I set up LTSpice to simulate the circuit. I don't have exact parameters for the Germanium transistors and diodes in the IBM SLT modules, but I used a model I found for an old Germanium transistor and hoped the results would be reasonable. I set it up to be initially in the reset state and applied a 100ns pulse to the circuit on the set side at +1 second. The flipflop switched as I expected it to, seen in the graph below:

Green is Q, blue is notQ outputs of the FF

The circuit I entered is here:

I used an initial condition to set the flipflop to its correct starting state. I applied a pulse using a voltage source at the bottom and simulated to get the graph above. I can now experiment with various defects such as too high a bottom voltage for the pulse to see if I can reproduce the failure to set the flipflop. If I can, I have a way to test various solutions for correct operation. 

Without the correct diode and transistor models, I won't get the same results as I am observing but it let me explore variations in the pulse voltage dip and the pulse duration. I didn't find much sensitivity to a shorter pulse; it worked down to a 3ns duration and failed at 1ns. 

It was more sensitive to the bottom voltage of the pulse. I could get it to fail at 1.9V and work at 1.8V or lower. These aren't accurate since the semiconductors aren't accurately simulated. 

Another idea I explored is that cumulative capacitance is slowing the fall of the signal so that the duration is what limits the bottom level reached. This can be capacitance on my PCB, in the cable and in the 74HC03 chip, in addition to the backplane and receiving circuitry of the 5804619 card. I bumped the capacitor up and watched the signal closely to see whether I could reproduce the shape. Higher capacitance actually made it less sensitive. 

I then dug through my documentation for IBM SLT and found some parameters that let me refine the models for the diodes and transistors in the circuit. The new circuit with the models is:

This is modeling the shape of the pulse I am generating with my board. I found that it would fail to switch at 0.9V but switch at 0.8V or lower, much closer to the failure point I was seeing on my scope. 

dark blue is the input pulse

Even with the pulse duration extended by another 50 nanoseconds, the flip flop will not turn on when the pulse only dips to 0.85V. It is much more sensitive to the low voltage than it is to the duration of the pulse since it is edge triggered. 

I then dug into the spec sheet for the 74HC03 chip that generates the pulse and see that it is current limited compared to the demands of the flip flop edge detector. By varying the series resistance of a voltage source, I recreated the observed pulse shape with about 1K of resistance, but the flip flop needs about four times that current to flip. Interpolating the spec sheet to the 3.3V VCC I am using gets me to about 3ma of sink current, which is close to the effect of the 1K series resistance in the model. 

HAVE TO FIND NEW CHIP TO DRIVE THE SENSE OUTPUT PULSES

The simulation suggests that I need about 10-12ma of sink current to reliably flip the register on. Initially I found that a 74LVC1G138 chip provides a single 2 input NAND gate with open collector and can sink 16ma on a low output with a max of 0.4V which would be excellent if I had designed with that originally. It would require a new PCB to implement, adding more than a week of delay.

The best fit would be a chip that fits the same footprint and pinout, but sinks 12ma and operates with 3.3V VCC. The 74LCX38 chip is exactly what I want. It has the same pinout as the 74HC03, operates at 3.3V VCC, and can sink up to 24ma with a low output. It comes in an SOIC-14 narrow package that is compatible enough to solder onto my board as it is.

Now the challenge - buying the SOIC-14 version is going to be difficult. Through Digikey, I can only buy batches of chips from a marketplace dealer - Rochester.  Mouser does not carry the SOIC-14 version at all. Rochester will not sell less than $250 at a time - even though the chips are less than a dollar each. The manufacturer, OnSemi, points only at Rochester as a distributor stocking any of them. 

Of course, Amazon and eBay offer a number of vendors in China who promise they will send me the chips. In my experience, almost every vendor from China is selling fake chips - sometimes they are just marked with the part number but don't work. In other cases, they take a similar chip like the 74HC03, bleach off the identifier and remark it as the chip I want. The chip inside still won't deliver more than 3ma, so that would be a waste of money. 

Based on this, I might be forced into the PCB redesign where I have several options for chips I can buy. I guess if I can verify the design works through some Rube Goldberg adaption right now, I could finish testing on the 1130 and then order the new PCB and new chips. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 2

WATCHING SIGNALS FROM THE 1130 TO THE BOARD

My first check was to watch the +StorageRead, +StorageWrite and +StorageUse signals as well as -BBit0 where I could verify that the LOAD mode of the rotary mode switch was delivering the intended bit value. 

I was missing one of the key signals, +StorageWrite,  from where I expected it to arrive. However I did see the -BBit0 signal do the right thing based on the console entry switch settings during a LOAD. 

The next test watched both a -Bbitx and a -Sensebitx line to verify their pullup to +3V when not activated. These were pulled up to 3V on the bit lines I checked.

PLUGGED IN MY BOARD, WHICH DID NOT WORK CORRECTLY

One of the symptoms was that the 1130 recorded a word with bit 10 on any time I did a DISPLAY, which flagged a parity error since my board was outputting the parity check bits based on whatever was coming out of the memory chip. These would always be correct which meant that the 1130 was detecting differently than I was outputting. 

I still had the missing +StorageWrite signal issue to contend with. I decided to test continuity of all the signals from the source gates in the CPU out to my board - all 16 -BBitx, all 16 -Sensebitx, the two parity check -Sense bits, and the three input control signals +StorageRead, +StorageWrite and +StorageUse.

CONTINUITY CHECKS OF THE SIGNALS ARRIVING ON CABLES T1, T3 and T4

The Automated Logic Diagrams (ALD) are the source I used to document the cable pins associated with each signal to the memory gate B-C1. I found discrepancies from what I expected! 

The +StorageWrite signal was only detected on cable T3 at pin J1 A11 which I had listed as a duplicate of the signal on H1 D11. When I tested the continuity between those two pins while everything was plugged into the memory compartment, they were tied together. 

However, the connection between the two could have been implemented in one of three places - the compartment holding the source gate could send its output to both pins, the cable itself would have tied the two wires together, or the memory compartment could have tied the pins together on the SLT board where the cable plugs in. 

With the cable disconnected from the destination SLT board in the memory compartment, the pins were not tied together, thus the connection was done on the memory compartment SLT board we are replacing. I chose the wrong pin of the pair that are connected in the memory compartment. 

In an ALD, the gate producing a signal has a list at the bottom of the page of every pin where the signal is connected off this ALD page. For the +StorageWrite signal, the gate producing it is AY on page MC101. The list of off page destinations was:

This only shows connections from compartment 01B-B1 where gate AY is situated to other pins on 01B-B1, not to the memory compartment. However, you need to understand that the locations in the top row of any compartment are the T1, T2, T3 and T4 cables that connect to other compartments. Looking at the cable drawing below we can see that the last two pins on the list are part of cable T3 that runs from 01B-B1 to 01B-C1 (our memory compartment. 

Thus the signal from gate AY in MC101 goes to pin H1 E11 of the memory compartment through cable T3. There it is also tied to pin J1 A11 but only on the SLT board in compartment 01B-C1 which we are replacing. I chose the wrong pin to route on my PCB. 

In addition to the control signal, which was a major error that blocked correct operation of my board for any memory access, there were five more signals where a pair of pins were tied together in the memory compartment yet I picked the wrong pin of each pair for my PCB. These are:

• -BBit0 which I assumed was B1 A09 but instead was only routed to A1 E09 on the cable
• -BBit10 which I picked from L1 A09 but was wired only to K1 E09 on the cable
• -Sense Bit 3 which I picked as B1 D11 but was wired to A1 E11 on the cable
• -Sense Bit 7 which I picked as C1 D11 but was wired to C1 A11 on the cable
• -Sense Bit 13 which I picked as L1 D11 but was wired to K1 E11 on the cable

I can tack a wire on the back of my PCB to hook the pairs of pins together as they are tied on the memory compartment SLT board, which will resolve the issues. In my defense, I saw the signal duplicated on the cable and picked the pin that fit the pattern of the others, but that was the wrong choice electrically.

You can see above how the -BBit0 and -Sense Amp Bit 3 pins I chose are in line with the others and fall into a nice pattern, while the first two instances at the top seem out of place. 

When I get back to the workshop, I will rework the back of my PCB to tie together the six pairs of pins where I chose wrongly - every single duplicate I found by the way. Then I will test again. 

Testing the 1130 MRAM core memory replacement on the IBM 1130 system - part 1

IT IS TIME TO HOOK THIS INTO THE 1130 AND TEST THERE

The three ribbon cables T1, T3 and T4 were disconnected from the gate B, compartment C1 backplane which houses the original core memory. These were inserted onto the connectors on my PCB. 

The red and black wires were connected onto the terminal strip TB2 just below gate B compartment C1 to provide the +12V power for my board. 

With that done, it was be time to power up the 1130 and check out the new memory.

TESTING ACCESS TO SOME WORDS USING THE LOAD FUNCTION

The IBM 1130 rotary mode control has a LOAD position, which uses the 16 console entry switches (CES) to input data and address values. I first set up an address on the CES then push the Load IAR button. This sets the memory address (SAR) to the chosen location. I change the CES to the data value I want to write into the chosen memory location and push the Start button on the console. This stores the value into the chosen memory location.

I put values into unique addresses using this method, then turn the rotary mode control to DISPLAY. In this mode, it reads the data in memory rather than writing it. First set up the chosen address on the CES and push Load IAR to select it. Next push the Start button to see the contents of that location display on the Storage Buffer Register (SBR) line of lights on the console.

RESULTS OF FIRST TESTS

When I attempted a DISPLAY the results were all zeroes with bad parity. I pulled out the oscilloscope to watch signals to see what is occurring. The line that I expected to see the +Storage Read signal appear was not changing. 

I will go home, review all the ALDs I have to ensure that I picked correct pins on the cables, then track down the exact issues tomorrow. I did verify that there were good voltages - +12V from the 1130 and +3.3V from the voltage regulator module - thus my board should be interacting. 

side project - IBM 3278 terminal restoration - planning for keyboard substitution

TERMINAL IS MISSING ITS ORIGINAL KEYBOARD

The 3278 terminals used the IBM beam spring type keyboards (type B), the most prized by keyboard afficionados for its feel. Thus keyboard pirates will find listings for devices like the 3278 and use only the keyboard. More often, recyclers or sellers of old gear will separate the keyboard as they can get 1-2 thousand US dollars for the keyboard itself. This leaves essentially useless terminals since the supply of keyboards has been hoovered up. 

The type B keyboard on the 3278 delivers a scan code in parallel on its interface for each key depression. These codes are associated with the position of the key-stem on the keyboard and therefore with the character printed on the keycap. 

The successor terminals like the 3178 made use of the 'type F' keyboard from IBM which is second best to the beam spring, but still desirable. Fortunately, not absurdly desirable and thus these can be found either together with their terminals or even separately for much more reasonable prices. 

The type F keyboard delivers a serial scan code, much like the later keyboards such as PS2, but the codes assigned to key-stems (and keycap characters) are different on most keys. It is feasible to read the scan code from a type M keyboard and translate that to a 3278 keyboard scan code, so that when the keycap with the character A is pressed, in the same key-stem position, the key code seen by the 3278 terminal will be the one that would have been sent by the beam spring keyboard. 

COMPLICATIONS TO DEAL WITH IN THE KEYBOARD SUBSTITUTION

The interface has wires for the seven bit scan code, power (+5, +8.5, -5, ground), power-on-reset, data available, make/break, keyboard ack, clicker, and four keyboard identifier bits. The identifier bits indicate the type of 3278 keyboard that was connected to the terminal. These include 75 and 87 key versions with different layouts. 

Many of the keys on the keyboard are called 'typeamatic', an IBM term that means if you hold the keycap down it will repeatedly emit that character, for example the space bar or a letter. Some are not. 

Some keys on the type B issue a different scan code for make (when it is pressed down) and break (when it is released) while most only issue one scan code. The type F indicates whether a keypress or a key release has occurred but we see both events. For the keys that don't have two scan codes on the type B, I can send only the make type scan code and drop the release. For those that will receive two scan codes on type B, I can map based on whether it was a make or break key action. 

There is an ALT button which changes the scan code issued for a key-stem. This only happens for the non-typeamatic keycaps; use of the Alt key involves emitting an Alt make code, the other key's scan code when it is subsequently pressed, and then the Alt break code when the Alt key is released - three scan codes emitted. 

The bottom right keycap (Enter key) is typeamatic on the type F but only emits one time no matter how long it is held down on the type B. I can resolve this by blocking repeated Enter scan code until a new character's scan code arrives from the type F. Since there is no Alt character assigned to this keystem, the fact that it is typeamatic and won't send the Alt make - Enter - Alt break sequence doesn't matter. 

The type F is a serial interface with one protocol, while the type B uses a parallel interface with a different protocol. I will need the two connector types and a microprocessor to handle the protocols on each connection, as well as handling the scan code mapping and other special handling mentioned above. 

Side project - IBM 3278 terminal restoration - looking into the high voltage power supply

REMOVED THE HV POWER SUPPLY AND OPENED IT UP TO INSPECT

The supply sits below the CRT inside the terminal. A connector brings 44VDC and a logic signal that disables the high voltage until the terminal logic is initialized and working properly. It also carries 400VDC to an accelerating electrode and a similar voltage to the focus electrode inside the CRT. A separate wire with a cap is plugged onto the side of the CRT to energize it with 18,000VDC. 

The supply consists of a small printed circuit board attached to a metal heat sink. The connector mentioned above, from the terminal, plugs into this board. Another connector has wires that go inside the metal box under the heat sink. 

Inside the metal box, I saw that everything was potted - sealed with a material that hides the parts underneath and keeps them from shifting about at all. This is helpful with very high voltages as parts that might shift due to handling of the terminal could come close enough to arc to other parts. The potting keeps all parts at their design distances. 

Unfortunately, the potting makes it very difficult to inspect, test or repair what is inside. A quick check with an ohmmeter shows infinite resistance between the anode cap and ground. I suspect some part has failed inside the potting resulting in a total lack of the 18KV power. 

THIS DOES NOT USE A FLYBACK TRANSFORMER FOR HIGH VOLTAGE

Most television sets make use of a flyback transformer to generate the high voltage for the CRT. The horizontal oscillator sweeps the beam across the tube, then at the right end of the line, the flyback transformer produces a powerful pulse to make the beam race back to the left extremely fast. This transformer also produces the anode voltage for the tube. If the horizontal oscillator is not running, there is no high voltage in this sort of design.

The 3278 terminal does have a horizontal oscillator which sweeps the beam across the tube, but it is not used to generate the anode voltage. Instead, as long as the 44VDC supply is present and the disable/enable logic signal allows the HV power supply to work, it will produce 400VDC and 18,000 VDC. It generates AC with an oscillator in the power supply, to drive transformers that step up to the target voltage. 

POTENTIAL SOLUTION FOR THE LACK OF 18KV POWER

It seems logical that the presence of 400V shows that the oscillator and driving circuits are working in the supply. It seems wasteful to create a second oscillator to drive the 18K stepup, thus it should be present since we have 400V coming from the supply.

This suggests to me that we have an open winding in the transformer or an open circuit in some voltage doubler components, but those are all inside the potting. If I can't fix that, I could install a replacement supply of 18KV. 

I did some quick checking and found availability of supplies that take 115VAC input and produce 18KVDC output, which would probably cost me about $100 or so to buy. I would add a method of disabling this driven by the disable/enable logic signal that does to the IBM HV power supply, thus my 18KV will only be delivered when the terminal is initialized. 

Before I commit to this, I should look at the outputs of the other circuitry in the terminal. If it is not producing scans and video output, the restoration might become unattractive. If I can see horizontal and vertical scanning plus a varying stream that would modulate the beam, then I could be more comfortable moving forward with the new power supply.

I will begin to plan the keyboard translator that will allow me to communicate with the terminal in spite of the fact that I don't have the 3278 keyboard - it was poached by keyboard pirates long ago. 

Success with the bench testing of the 1130 MRAM memory board finally

FINDING ROOT CAUSES

I have been plagued with erratic results, non-repeatability and other challenges in what should have been a straightforward verification of the correct operation of the memory replacement board. I began to suspect that the bench testing apparatus was causing these issues, not the board or its components. 

The Arduino had 16 data outputs and 13 address outputs that had to be connected to my board, in addition to the control signals that drive the read and write operations. For each of those lines, there was a male pin on my board and a female socket on the Arduino, which I connected with a M-M jumper plus a F-F jumper to change the gender. That means 3 connections for each of the 29 lines, none of them mechanically secure. 

I also used alligator clip jumpers and pin jumpers to connect grounds between the Arduino and my board as well as connecting to a breadboard where I had the pullup resistors for the sense output lines of my board. The Arduino ground is just a few pin sockets. I believe that slight vibrations were causing noise or corrupting signals as this setup was just too fragile to trust the results. 

FIXING THE ISSUES

The writing program was changed to perform a read back of the address right after the write cycle. I pulled all the address lines off as I already know it was correctly addressing memory, thus all further testing was done just with location 0. That eliminated 13 signals and 39 connections. 

I moved the 16 data connections from the Arduino to the breadboard and set it up so that a slide switch would set the data to 0 or 1. The Arduino was only emitting the Storage Write and the Storage Read control signals now. 

TESTING RESULTS

I was able to verify that all 16 sense output lines were producing the data that I had just written, reliably. I checked the checksum output lines as well and verified that they were giving me the pulses needed to achieve odd parity on each 8 bit halfword coming from memory. 

I am now satisfied that this works properly, so that I can attach it to the 1130 system and test it there. 

The board above with its bodge wires and the outboard voltage regulator module needs conformal spray and then a metal can placed over the MRAM chip to reduce stray magnetic fields that might change the data stored on the chip. 

side project - restoration of IBM 3278 terminal - some debugging

ALL LOW VOLTAGE SUPPLY LEVELS ARE GOOD

The LV power supply produces a range of voltages for the digital logic, memory chips, analog logic and to power the High Voltage (HV) supply. I verified the presence of +5, -5, +8.5, +8, -12, -44 and +44 VDC as well as the 6.3VAC for the display tube filament. 

SOME OF THE HIGH VOLTAGE IS WORKING BUT NOT ALL

The HV power supply produces voltages such as 400V for accelerating the electron stream towards the front of the screen - those are present. However, the tube needs a really high voltage to produce a nice bright image on the phosphors. The supply is NOT producing the 18,000V which is why the tube isn't showing anything. 

NO SCHEMATICS THUS I WILL HAVE TO REVERSE ENGINEER IT

If I figure out enough of the circuit to figure out why it is not generating the very high voltage, I might be able to fix it. That assumes that it is a repairable part or that I can find a compatible 18KV supply from an oscilloscope or similar CRT device. 

side project - restoration of IBM 3278 terminal - inspect, mechanical fixes, first power on

REMOVED COVERS AND LOOKED OVER THE TERMINAL

The covers were set aside and I could then see everything inside. The terminal looked complete and nothing was obviously damage inside. 

MECHANICAL TWEAKING OF FRAME AND HOLDERS

The covers and the mounts inside had been twisted and loosened, although based on the pictures posted from eBay this may have happened before shipment. I straightened them as well as I could. 

More work on bench testing for the 1130 MRAM core memory board

IMPLEMENTED BACKFEED PROTECTION CIRCUIT

I put a through hole IRF540N MOSFET on the prototyping tool breadboard, isolating the ground of my PCB until a voltage divider from the +12V bench supply feed is active. This low side isolation ensures no back-feed current will flow from the Arduino or any other input to the board unless we have our power turned on. 

REPLACED ONE OF THE BUFFER CHIPS ON THE BOARD

I had lifted a 74LV240 inverting buffer chip from the PCB while investigating the observed steady 1 voltage on the bit 14 net that had been producing a pulse on sense bit 14 for any and all addresses. I put a spare chip on the board so that I can write zero and one values to verify the memory chip is working.

I RESUMED BENCH TESTING BUT STILL HAVE POWER ANOMALIES

I checked to see if there was any back-feed voltage on the PCB with the Arduino active while I was not feeding voltage from the bench supply to the board. I used an ammeter on the ground line that passes through the MOSFET. After this was validated, with no current until I triggered the MOSFET, I thought I was ready for function testing. 

However, strange things are still happening. When I power the board from the bench supply, there is no indicated amps or watts being consumed when the MOSFET is connected. When I disconnected the MOSFET, I saw about 7ma of draw on the supply! At first I thought it might be my pullup resistors for the scope probes when monitoring the sense output pulses, but with those disconnected I still had 7ma flowing somewhere. 

I pulled the USB connection for the Arduino Due and my current disappeared! The Arduino is pulling current which is very odd since I have nothing but output pins defined on the Arduino. It isn't backfeed - it occurs when the Arduino is powered, not when it is getting power from my board. In fact, my board's outputs are open collector, with pullup done on the prototype breadboard (disconnected) not by my PCB components, so there is no voltage that should flow from my board to the Arduino configured in output mode - at least I don't expect there is any. 

I am going to disconnect groups of pins from the Arduino and monitor the current draw while my MOSFET is isolating my circuitry, until I get more of a clue to where this power consumption is going. The 12V from the bench supply flows through a regulator module to create 3.3V first, which means the draw is larger on the 3.3V rail than what I see on the bench supply. 

IMPROVED BENCH SETUP TO MONITOR PINS OF SMD CHIPS ON MY BOARD

I found it cumbersome to tack tiny wires on the pins of various chips in order to observe the signals during read and writes, so I pulled out my PCBite and put my board on that. This has probes with teeny pins suitable for measuring a surface mount chip pin, held in place with magnets onto the base plate. With my board anchored and the four probes set up, I could watch different pins as I study the function of the board in more detail. 

Using LT SPICE to study back feed voltages from digital inputs when power supply not operating

BACK FEED ISSUES I WANT TO AVOID

Digital abstractions for logic gates and other chips mask the analog reality of those devices, where the components inside have complicated behaviors that can produce results in the real world that don't exist under the abstraction.

For example, a NAND gate with two inputs and an output can feed power into its own chip and all the others on a board if the input to the gate is powered but the board is otherwise not powered. I would observe the board producing outputs but I hadn't turned on the bench power supply yet. 

This occurs because the input circuits of the NAND gate has protective diodes on the input - one of which will pass the power from the input to the VCC pin in the unpowered gate, powered input case I mentioned. That input pin is then providing all the current demanded by the chips on the board. The chip can easily be damaged because of that. There is even the chance that the power demands of the input can be more than the driving device (an Arduino Due in my case) can source, damaging the Arduino.

I set up a MOSFET to interrupt the low side (ground) of the board if the bench power supply isn't delivering voltage to the board. With the ground of the board isolated from the ground of the Arduino Due or other source to the input pins, no current will flow. 

The MOSFET is a complex device in reality, as is the voltage regulator providing the 3.3V from the 12V of the bench supply. Therefore I wanted to examine the real world behavior of these to see whether there is any back feed voltage and current pulled from the 

RAN LTSPICE SIMULATION OF THE BACK-FEED PROTECTION

I set up a schematic with the MOSFET circuit I will use for isolating the low side (ground) of my PCB. A diode representing an input protective diode on a logic gate as connected to a 3V voltage source to represent the source of back-feed. I then modeled the current flowing through my PCB circuits (represented by a simple load resistor in this model) while I alternated the control signal between 0V and 12V. It worked exactly as I expected, ensuring virtually no current flowed from the powered input pins of my PCB until the +12V was present. The simulation showed nanoamps of current flow due to the non-ideal nature of the MOSFET, but that is negligible.

I then set up a schematic with the LDL1117 voltage regulator I intend to use on future boards to replace the outboard voltage regulator module, dropping the +12V (or slightly higher) down to 3.3V for the chips on the board. I modeled what happened with the input pins of the board driven by 3 or 3.5V while the regulator chip was unpowered. I saw a slight voltage and only microamps flowing out of the regulators power input. This is insufficient to energize my MOSFET to connect the board ground to the grounds of the rest of the setup. 

Side project - restoration of IBM 3278 terminal - shipment arrives

QUICK LOOK AT THE OUTSIDE OF THE PACKAGE

It was delivered today. The box is a bit beat up but intact. More importantly, I don't hear any tinkling of broken glass which is a good omen for the condition once I open it. 

BROUGHT TO WORKSHOP FOR FUTURE WORK

I will set it up next to its 3178 and 3179 brethren on a table in the shop. I have a 3174 controller and other equipment which will allow these to be connected to my P390 system allowing me to interact with IBM mainframe software via real terminals. 

First thing though is to unpack the box and assess the condition. I have guests visiting for a couple of days but when they have left I can get to it. 

Bench testing of the 1130 MRAM core memory board still not successful

MODIFIED THE CONTROL SIGNAL DESIGN OF THE BOARD

I had noticed that the data bits being passed through the buffer from the B register did not settle rapidly due to capacitance in the circuits, both on my board and the bench test setup. With a pulse width of 80 nanoseconds for both buffer enable and write, I was concerned that the data was not properly set up on the MRAM chip pins by the time the chip locked the data in for the write. 

The chip enable signal ~E is unchanged. It is asserted low when we have both +12V supply from the 1130 computing system and the Storage Use signal from the 1130 is asserted. 

The chip write signal ~W is unchanged. It is asserted low when we have Storage Write asserted and the write timer produces its 80 nanosecond pulse. 

The chip output enable signal ~G that drives the data output pins is asserted low when Storage Write is low.  During the read part of a memory cycle, Storage Read is asserted high and Storage Write is asserted low. 

The buffer enable control signal ~IO is asserted low when Storage Write is asserted high. 

The sense output pulses occur when the read timer pulse is active, some time after Storage Read is asserted. This is unchanged. 

I had to cut traces and apply bodge wires to implement the new scheme with the existing board. Due to traces passing underneath chip U14 where the control signals are generated, I had to temporarily remove the chip, modify the board and then solder the chip back down. 

Traces cut underneath chip U14

Trace cut to ~W pin on MRAM chip

Bodge wiring added

REDID THE WRITING PROGRAM AND THEN OBSERVED THE READING

The writing program was changed to loop through all of memory, storing a data value equal to the storage address in each word. The reading program now takes input over the serial monitor with an address to read, thus allowing me to read any desired address while observing the output pins. 

I could check the various addresses that are powers of two, verifying that only the sense output bit that matched the power of two from the address would be 1, with all others producing no pulse. Some random addresses that were not a power of two could be read to check the appropriateness of the sense output pulses. 

Lastly, I scoped the two parity output bits to see that the correct bit was output for each of the selected addresses. The board produces a parity bit to provide odd parity for each halfword (eight of the sixteen data bits), so that the number of pulses being produced in that halfword is an odd number. 

When the output word is zero, for instance, both parity bits should pulse to provide correct parity. With the values I am reading, there is only one bit that is 1 so the halfword that contains the bit should have no pulse on its parity line while the other needs to pulse. 

TESTING ON THE BENCH AFTER THESE CHANGES

I ran the new memory write program on the Arduino to configure the MRAM memory. I then started checking with the new memory read program and the oscilloscope. All bits came back as 0 for any address except for sense bit 14 which always returned a 1 pulse. Checking the static voltages showed that with the ~G signal asserted to output the memory contents, the net for bit 14 was at logic 1 level. 

It wasn't clear whether the MRAM chip was driving the 1 or that something else was wrong. If the 74LV240 inverting buffer chip was malfunctioning, it might be forcing output in spite of its control signal ~IO being at logic high (disabled) so that it should be in high impedance mode 

I then did a static check on ~IO to confirm that it was at logic high. I checked both of the 74LV240 chips, one for each eight bits of the word, to see if the results were different on the other half of the word. 

I was able to successfully load various patterns into bits 0 to 7 of some memory locations, thus confirming that the basics of my design work. However, bit 14 continues to show a high value regardless of what data is written there and for any memory address. 

One other issue I detected was that the parity generation process is now producing a check bit regardless of the number of 1 bits in the half word. 

As a final test of this possibility, I removed the 74LV240 chips from the board and did another set of read tests. There should only be outputs driven by the MRAM chip on the nets, thus sense bits should all reflect what the chip is emitting and nothing else. Bit 14 remains high while the others are not - that could be because I have written a 1 into all the addresses due to a defect in the removed chip, or it could represent a failure in the MRAM chip. 

POWER BACKFEED DIFFERENT FROM THE ORIGINAL LAPTOP CHARGER CASE

I noticed that the sense output pulses were being produced by the board but the power supply to the board was turned off! This highlighted that my bench testing setup is backfeeding the board through the protection diodes in the chips. That is not good. The current flow from a backfeed can damage the chips on the PCB. 

NEED TO RETHINK THE TEST BENCH SETUP - PLUS SWAP ALL THE CHIPS AGAIN

The setup I had been using has a prototyping breadboard setup that I used to implement the pull up resistors for the sense output lines. It had a main power supply to the PCB, with a bench supply delivering 12V that is then regulated down to 3.3V for the chips on the board. Finally, there is an Arduino Due that is being powered through the USB cable from my laptop. 

The Arduino is producing 3.3V logic high signals which I suspect is the cause of the backfeed of power. The prototyping setup has 3.3V but that is connected to open collector output chips on thus board thus not causing backfeed. 

There is one final vulnerability in my design. I  drop the 12V power coming from the bench supply (and eventually from the 1130 CPU) down and apply it as a logic input to produce the memory chip enable signal. This is a potential backfeed through the input of the logic gate if the 3.3V regulator output is not present or lower than the voltage divider result. 

I have ordered a full set up chips for the board in order to replace anything that was damaged during the testing regimen. This will take about a week to arrive, after which I will install them and begin testing with a new backfeed safe setup. 

BACKFEED PROTECTION WORKED OUT

To avoid backfeed, I can't have any voltage on a input that is higher than the VCC supply voltage and those voltages to inputs must absolutely not be delivered unless the board's power supply is active. 

I could power the Arduino through a MOSFET so that when my VCC is off, the Arduino is off and not supplying any power to input pins. That means it must not take power from the USB port, only through my MOSFET supply; generally that means a modification to the Arduino board. 

There remains the production use case where the IBM 1130 +3V power rail is active but the +12V is not active, either during power-up and power-down or due to loss of the other 1130 power rails. This will be pulling the inputs up to +3V and backfeeding power to my board. I need a solution to this, ideally one that does not require 29 sets of parts for the protection. 

The solution is to use a MOSFET to isolate the ground to my PCB unless there is the +12V supply available. When no +12V exists, the board is isolated from ground and this eliminates any power flowing into the board from the B reg or SAR inputs. It also blocks the +12V resistor divider from dropping the 12V but since the ground is isolated this doesn't inject power into the gates. 

This solution allows me to use the USB power to the Arduino without any modifications, since my board is isolated from the Arduino when VCC is not delivered to my board because my bench supply is not delivering the +12V to the regulator and board. 

Restoring IBM 2501 card reader - more focus on the stacker side of the mechanism

DISASSEMBLED THE STACKER AREA AGAIN TO GET ACCESS TO ROLLER

The small roller that pinches the card being ejected into the stacker was found to be frozen in my last session. To get to it, I had to remove the stacker hood, the curved arch and cover that directs the card upwards to the stacker, and then remove the rest of the stacker mechanism.

Curved arch and rest of stacker mechanism removed

I pulled the roller part off the mechanism and began working on clearing up the issue. I flooded it with clock oil and manually turned the roller. It was very stiff and crunchy, but with lots of oil and manipulation until it finally began to roll easily as the bits of dust in the ball bearings were flushed out. 

I found two levers on the underside of the joggler structure that were designed to pivot but were stiff due to old lubricants. I don't see what will cause these levers to pivot since they don't connect to any other parts in the mechanism. However, I worked oil into them and manipulated them to make sure they would pivot freely. This took quite a bit of time as well. 

I also tested card movement through the rest of the machine and found that the drag on a card coming in from the hopper was a bit high. The metal surface of the machine that the card will be pushed over had bits of crud on the surface from all the rodent deposits. 

I was able to partially clean it by using a stiff brush along with a cleanser (409) but will have to do more work to get this completely cleaned off. I will finish the cleaning at my next workshop session, along with reassembly of the stacker mechanism parts that I had worked on today.

1130 MRAM board - failed chips identified and replaced

LAPTOP CHARGER IMPACT ON ARDUINOS

I have experienced odd behavior with multiple Arduino based items, where plugging my laptop charger into the outlet causes the Arduino and its connected signals to malfunction. The Arduino has to have its ground pins tied to the a ground of a device plugged into the AC mains. Somehow the laptop does a weird change to voltages seen on the Arduino in this case, perhaps it drives voltage onto the ground connections to the other device. 

I did see this again when I was bench testing my MRAM core memory replacement board, using an Arduino Due to produce the address, data and control signals to the board. The bench powers supply delivering 12V to my board would sometimes show zero current flowing, which I suspect was a consequence of power flowing into the regulator device or the bench supply. It also disrupted the behavior of the Arduino program and made the traces on the oscilloscope move up a bit. 

SUSPECTING THE LAPTOP CHARGER ISSUE FRIED ONE OR MORE CHIPS

Much of my board is still working - the internal control signals that drive the MRAM memory chip to read or write, the timers that produce a pulse around 800 ns after the Storage Read or Storage Write input control signals go high, the XOR chain that calculates odd parity, and the NAND output gate that emits a pulse for the two parity bits. What does not appear are any of the 16 data output pulses from NAND output gates. 

I didn't know if the MRAM chip itself had failed, or the NAND output gates for the 16 bits had failed, or the inverting buffers that route the B register inputs to the board onto the memory chip during write had failed. I tacked some wires on pins on the suspect chips so that I could positively identify any malfunctioning parts. 

RESULT OF THE TESTS - WHAT WAS DEFECTIVE

I saw the input bit being driven onto the memory chip data pin during the write, and confirmed that all the control signals were good for the chip to perform a write. I then starting the reading program and saw the memory chip data pin outputting noise when the chip was enabled to output the data that was read. 

The address line for location 1 is the blue trace that I triggered on. The yellow line is the control signal to the memory chip to output the data bits. Green is the sense output line that would pulse downward if the data bit was 1 and purple is the memory data pin itself. The output should go high if there is a 1 in memory at the selected address, but it is low. Within 35 nanoseconds of the Storage Read control signal, the chip should have resolved the contents of the address set up by the address lines (blue), then when the output is enabled (yellow) the result should be output on the data pin (purple). 

I determined from this that the most likely failed part is the MRAM chip itself. Secondarily and much less likely, it could be the NAND gates if they failed so they short their inputs to ground, which I don't believe is the case. 

I saw that some bits were working properly and producing output pulses while others were not. I tacked a wire on another data pin of the MRAM chip and saw similar results - data was gated to the pin during the write process but did not come out during the read process. 

ORDERED REPLACEMENT PARTS FROM DIGIKEY

I placed an order for the MRAM and four of the NAND gate chips which I received this week. I put them on the board and resumed testing. 

Restoring 2501 reader - linear bearing repair, still one roller bearing to resolve

MANAGED TO FREE UP THE BALL BEARINGS IN THE STACKER SLIDE

Previously I had despaired of getting the slide in the card stacker to move freely enough to be usable, due to corrosion in several places, particularly on the rod and linear bearing upon which the slide travels. I was able to inject the clock oil into the ball bearings inside the shaft of the linear bearing. This returned them to smooth operation. 

The rod is still a bit rough so the smoothness is not perfect but seems sufficient to have me stay with the IBM parts. I got everything reassembled and did some testing. It is borderline, but I may be able to relieve more friction on the rod, the flat spots on top of the slider and the underneath of the side rails that the flat spots slide upon. 

CHECKING CARD PATH AGAIN FOUND ONE ROLLER NOT TURNING

While hand cranking the mechanism, I tripped the solenoid to watch a card be fed from the input hopper into the pre-read station. It didn't reach the full end point but I believe the reader depends on the momentum of the card to continue its motion once it exits from the pressure rollers. 

I then tripped the other solenoid and cranked the card through the read station and up into the stacker. It paused partway through the stacker where I realized that I had a problem with one roller. A rubber wheel turns on one side of the card while a spring loaded metal roller pressed on the backside of the card. The wheel turns but the roller did not. 

roller circled in red

I began treating it with clock oil, but t may require removal from the machine to really get it working smoothly. We will see how it turns on my next visit to the workshop, otherwise I will partially disassemble the stacker once again to get that roller out. 

STACKER JOGGLER FUNCTION VERIFIED

The jogglers grab the bottom edge of a card that has fallen down after ejecting from the reader, moving it over against any other cards that are already in the stacker (or against a metal holder if this is the first card going into the stacker). The joggler linear motion is provided by a pivot that rides on a cam, but the pivot was almost frozen in place.

I forced the pivot off its shaft and removed some crud. There was a bit of corrosion near one end, but fter greasing the shaft and reassembling the mechanism, I observed very smooth and easy movement. 

Restoration work on 2501 card reader - card path and stacker

CLEANING OUT CARD PATH INSIDE THE READER

Once a card is fed from the hopper into the card reader, it sits in the pre-read station until a solenoid presses a pinch roller onto the card to push it into the read station. The read station senses the holes in each card column as the card moves through it, driven by a roller pair pinching the card. The card is then moved up a curve into the stacker, where it will be ejected, then fall down to join the other cards already in the stacker. 

I fed one card from the hopper and encountered resistance. From this I looked for and cleared out some crud in the path so that the card can enter properly and come to a stop in the pre-read station. 

I then depressed the solenoid lever to start feeding the card into the read station, but it wouldn't move through the station. Testing with an edge of a card showed me blockage inside the throat of the read station. 

Read station, card moves through from left to right

The read station consists of a lamp at the top, twelve fiber optic cables which feed the light uniformly to the twelve row positions of a punched card. Underneath there are twelve photocells which detect the light when there is a hole in the card at the current column, otherwise they are left in the dark. I found some rodent paste (urine, dust and feces) that was built up over the top five rows of the photocells. 

Photocells

Light guides and roller

Once that was cleared up, I started a card moving from pre-read through the read station but it was jamming at one side in the curved guide just after the read station. Opening up the guide, I found some crud along the edge of the path. It was cleaned out and finally the card could move all the way from pre-read, through the read station, through the curved guide, and up into the stacker. 

Location of the gunk

Arc redirecting cards upwards into stacker

Inside stacker from left side

STACKER CORROSION KEEPS SLIDE FROM MOVING SMOOTHLY

The stacker is where cards are stored after they have been read. The card is accelerated out of the reader in an upward arc into the stacker, where the front edge of the card strikes a rubber bumper on the top causing the card to stop and fall downwards. 

Jogglers move back and forth at the bottom of the stacker, moving the card that just fell to the left of the machine so that it is up against previously read cards. A metal support on the left is what the cards are stacked against. 

As the number of cards in the stacker grows, the metal support moves leftward. It is on a slider that moves along a rod under the stacker, with spring pressure pulling the slider to the right so that it only moves leftwards as cards join the group in the stacker. 

The slider has a linear ball bearing on it that moves over a steel rod. The rodent urine and other contaminants have pitted the surface of the steel rod and frozen the ball bearings. The slider will not move freely nor reliably be pulled to the right by the spring. 

I tried to smooth down the rod but the bearing itself is shot. I now have to replace the slider bearing and perhaps the rod as well. The rod fits into holes on the right and left sides of the stacker, with a groove on the rod capturing a C clip to keep the rod in place. 

Slider on left, bearing removed and on the right

Groove on the rod

The top of the slider is held down by metal plates running horizontally across the stacker. The top of the slider and the underside of the plates also has some corrosion but I believe that can be resolved. 

Side project foiled - restoration of an IBM 3278 terminal

FOUND A 3278 TERMINAL ON EBAY AT REASONABLE PRICE

I saw a terminal being offered on eBay which appeared to be reasonably complete other than it lacked the keyboard. For most people, without the keyboard this is useless which accounted for the relatively low price. 

The keyboards used with the 327x terminals is highly prized by keyboard pirates, people who buy these to adapt them as a PC keyboard because of the better feel of the keyboard. They will separate keyboards from their terminals since they have no interest in the terminal itself. This results in a terminal without keyboard that almost nobody could use. 

As a result historical devices like the 3278 are turned into scrap. Even mainframes, for example the IBM 4381, which use a special version of the 3278 as its system console, are make unusable without a functioning 3278. 

I made an offer which was accepted for the 3278, offered by a respected volume seller in Canada who packed it up and shipped it off using UPS. It was projected to arrive on September 9th, although there may be customs delays and I might have to pay some nominal duty for the package.

PLANNED TO BUILD A INTERFACE CIRCUIT TO USE 3178 KEYBOARD

I could not find any schematics for the 3278 itself, but felt there was a reasonable chance I could get this working. The other issue which kept most people from buying this was the lack of the keyboard.

I have found enough information that I should be able to generate the proper signals to the keyboard cable for the terminal to believe the physical keyboard is attached and works. I also have a spare keyboard for an IBM 3178 terminal. 

I believe I can build a device that will connect to the 3278 keyboard connector and have the 3178 keyboard plug into it. I can transform keystrokes and modify the signals to make this work. There is a mismatch between the keys available on the 3278 and on the 3178 keyboard I own, but I can pick keys to sacrifice, mark them as the intended 3278 key, and map the codes to produce the 3278 keycode when my chose 3178 key is pressed. 

LOST OR DUMPED IN A RAVINE BY UPS CANADA

I watched the package move from its origin in Alberta to a warehouse in Calgary early on September 3rd. The tracking system marked this as waiting in a secure facility for resolution or clearance. After four days with no movement, I called UPS who assured me that there was no missing information needed for it to continue movement; it was just waiting for customs processing. 

September 9th came and went with no change in the tracking. The seller contacted me and said that UPS told him that he should file a loss claim as it appears the package has disappeared. He told me that he has had several packages heading from Canada to the US disappear the same way - he speculated it had something to do with the tariffs. 

One can imagine a mountain of ignored packages while UPS Calgary avoids dealing with confusing tariffs. Since these are assessed by US Customs staff rather than UPS, there is no reason they should avoid passing this along to Customs.

There could be a mountain of ignored packages while US Customs in Calgary is totally overwhelmed. 

There could even be scenarios where employees annoyed at US tariffs and recent political actions are dumping packages going to the US. 

Finally it could just be plain incompetence. 

In any case, with the claim being filed by the seller, even if they find it they will not send it onward as insurance would now own it. I will get my purchase cost back, according to the eBay seller, but the 3278 is lost not only to me but to anyone interested in restoring it. 

Side project - restoration of Sony VP-5000 U-Matic tape deck for Space Force Museum

BOUGHT USB VIDEO CAPTURE DEVICE AND VERIFIED THAT IT WORKS

Connecting the video and the stereo audio output from the deck to a PC or Mac using USB, this captures the recordings and produces MP4 format files that can be further processed and archived. I will donate this to the archives and we will install the open source OBS software that does the actual capture and encoding using the USB device. 

MAY NEED TO BAKE TAPES BEFORE PLAYBACK

The sample tape I used to restore the deck didn't shed much oxide nor did it have layers sticking together, but that is a common problem with old tapes which may impact other titles in the archives. The solution is to bake these for a couple of days in an oven at low heat. We will need to look over the tapes to decide which need this treatment.

Side project - restoration work on Millivac MV-864A meter, part 3

PERFORMED ADJUSTMENTS AND CALIBRATIONS

The service manual provides a sequence of adjustments, mostly using an oscilloscope and various trimmer potentiometers to zero out the various amplifiers and detectors in the device. I worked through them methodically and the result is a meter as good as it was when new. 

Side project - restoration work on Millivac MV-864A meter, part 2

METER DOES NOT MECHANICALLY RESTORE ALL THE WAY TO ZERO POINT

The meter on the face has a screw that changes a coil spring tension to make the pointer align exactly with the left side (zero) position of the scale. Moving the screw will move the pointer further away or closer but it never gets all the way to the zero line. Not sure what I will be able to do about this.

DECIDED TO CHECK POWER SUPPLY VOLTAGES AND OTHER CHECKS OF THE CIRCUITS

I opened the meter, with the expensive manual I purchased, looking for the test points listed for the +8.5, -6 and other voltages. The first thing I noticed is that the board shown in the manual does not look like my board. The one in my meter is larger and includes the resistor networks for the range switch. 

More importantly, it has no test points labeled TP1, TP2 and TP3. It does have points such as TP63, TP61 and TP62, but they are tied together or otherwise don't make sense as the place to check the supply voltages. 

The schematic shows five transistors, five diodes and a bunch of passive components for the power supply, but mine had only two transistor looking objects. The schematic has silicon transistor numbers on it, but my board has an obsolete germanium MHT3030 power transistor made by GPD Optoelectronics and a GE RA1 three lead component. 

I was able to track down an old GE manual and found the RA1 as a reference controller for power supplies, consisting of a germanium transistor and a zener diode encapsulated in a single TO-5 style can. The GE manual showed me an example circuit which matches decently with the connections I can see on my meter's board. 

I am reverse engineering the power supply part of the PCB in my meter - components that start with a 6 such as R601 or C602. The power transformer and the primary side circuit match well, but it diverges on the output side. The transformer has a long winding with three taps between the two ends. The center tap and the two outer connections are fed through a pair of diodes (half wave rectifier) in both the schematic and in my board. If you number the secondary wires as 7, 5, 8, 6, 9 then the center tap is 8 and the ends are 7 and 9. 

On the schematic, 5 and 6 are unconnected. The pilot light is powered from a resistor off the output of the two diodes. Yet, on my meter, windings 5 and 6 are connected to the pilot light, driving it with AC. 

I am carefully reverse engineering the power supply as it exists on my meter, drawing it out and noting parts values. I will then check whether it is working as intended and make adjustments if necessary. That will happen in a later workshop session. 

I paid a relatively high price for the manual from the manufacturer, who used my serial number but didn't have a version of the manual old enough. The sent me the oldest version in their files, which as I mentioned was in the silicon semiconductor era while mine is an old design using germanium devices. I suspect I will find many differences in the rest of the manual and schematic as I work on this project. 

More Bench Testing of the 1130 MRAM memory board

FLAKY BEHAVIOR OF DIRECT PORT MAPPING OBSERVED

I ran the program to load the memory and happened to put a scope probe on the Storage Write signal which I should be toggling on for each of the memory locations, but saw the signal stuck steadily at high. In some other cases I saw results that didn't match what I expected from the program to read memory.

I switched back to digitalWrite from the direct port access just in case there was something going on that I didn't understand with port access on the Due, which has an ARM chip rather than the usual Arduino processor type. 

 However, in retrospect this is due to the weirdness that occurs when the laptop is plugged into the wall using its power brick. Running just on batteries should eliminate these gremlins. 

NEW PROGRAMS LOADED INTO ARDUINO AND TESTING RESUMED

I ran the loader program that wrote the values 1, 2, 4, 8, 16 . . . 8192 into locations 0, 1, 2, 4, 8, 16 . . . 4096. These locations and values were chosen to have a unique wire I could monitor for each choice. This simplified triggering and monitoring on the oscilloscope.

I saw the B register inputs set low for the desired address and the board was generating the inverted write control signal that causes the MRAM chip to write the data into the selected memory location. The control signal is applied for a bit under 100 nanoseconds and the B register data is gated through to the memory chip at the same time. 

However, when I then ran the reading program (below), all outputs were 0. I could clearly see the address and the B register inputs were correct and all the control logic signals on my board worked properly for the writes. The address and all control logic signals were correct on my board for the read, yet the data was not the 1 value I expected. 

My XOR logic is producing a 1 for each of the two check bits and those pulses are emitted correctly during the reads. Earlier I had seen outputs that were 1 but my guess is that the strange power injection when my laptop is on AC power, through the Arduino, has damaged one or more chips on my board. 

Possible bad chips are the MRAM memory itself, the buffer chips feeding it the B register data, or some of the open collector NAND gates that pass along the pulse for any 1 bit read. Once I pin down the failure further I can replace parts and resume testing. 

NEXT SESSION PLAN

I will tack wires on the data bit 15 pin of the MRAM chip and on the input to the buffer that feeds the B register values to the chip. Using the scope, I will be able to verify that the B register value reaches the buffer and is passed through at the proper time to the MRAM pin. I can then look at the MRAM chip pin when doing a read to see if the 1 bit is making it back out. I will also be able to see if there is a 1 coming out of MRAM on a read but no pulse out of the NAND gates.