More work on retriggering issue with 1130MRAM

GOOD SUGGESTION FROM A BLOG READER

One of the blog readers, Merlin Skinner-Oakes, suggested that I add a low pass filter to the output signals that are causing the ground bounce. These are the eighteen sense bit outputs, open collector gates which pull the line to ground and sink around 8ma for every bit in the word or parity that has a value of 1. The more 1 bits in a word, the worst the retriggering. 

I had to choose a chip that could sink 8ma on every output, would be gated by the pulse from the second read timer chip, has an open collector (drain) output, and would operate properly at 3.3V. The selection was slim. The chip I chose has a very fast edge, compared to the SLT logic in the 1960s era IBM 1130 system. 

The initial values to test were 100 ohms and 100 pF, to see if slowing the fall time of the signals would lessen the problems. This establishes an RC time constant of 10 nanoseconds, thus the falling edge is spread over very approximately this time instead of falling very steeply. I can adjust these component values as necessary to fine tune if the initial results seem promising. 

BODGING THE CURRENT BOARD TO TEST THE FIX

The lines run directly from the surface mount output chips to the SLT connector cable pins. I will need to break the connection between the chip output pin and the cable connector pin in order to insert a resistor in line and a capacitor to ground. I would need to cut the traces on the top layer coming out of each chip, then run bodge wires from the relevant pins to my RC filter components.

This would be very messy to do with eighteen output pins and bodge wires to 36 discrete components. Instead I will test this with the minimum changes by altering only the two parity bit outputs and using a word of all zeroes. That will only produce pulses on the two parity bit lines, as these must have a 1 value to achieve odd parity. 

First two bodged RC filters on parity outputs

I just had to cut two top traces coming out of chip U11 to disconnect output pins 3 and 6 from the connections up to the connector cable pins. I then tacked on two wires at pins 3 and 6, connected them to an RC pair each, hooked the other end of the resistors to the T4 connector cable pins L9 and L10 and hooked the other end of the capacitors to ground. 

I had many frustrating setbacks with this work - it was extremely easy to form a solder bridge across the surface mount chip pins. When wicking the solder away, it was easy to break the link to the pad invisibly, so that a connection appeared good but was not. Solder could form shorts underneath the chip, not visible to the microscope. I even tacked a wire onto the wrong pin in one case. 

Each time I had to pull the board and do work at the soldering/rework station. Every manipulation threatens to break off tacked wires. I persevered until I had the board ready for its testing. 

TESTING RESULT

I had to store a word of all zeroes first, then perform a display of the word to see whether the spurious retriggering and ground bounce is suppressed by the RC filters I added to the outputs for the two parity bits P1 and P2. 

Initially I had more problems with solder joints as I worked on the chip to add the bodge wiring - one of the parity bits wasn't working due to such an issue. I finally got all signals connected properly with no shorts.

I was not seeing the parity check bits in the IBM 1130 being set by the sense pulses after they passed through the RC filter. The circuit that sets the flip flops depends on the falling edge of the signal to discharge energy in a capacitor. Previously with a prior output chip I found that the flip flop wasn't being set because the output chip couldn't sink the 8ma of current to cause the edge pulse in the 1130. 

In fact, the resistance of the RC filter lowered the current enough to either prevent the flipflop from setting or cause it to only set sometimes. I had to cut those out of the circuit to restore the setting action. 

GROUND ISSUES IN THE PCB ENTER THE CROSSHAIRS AGAIN

I did more measurements of the ground voltages on the PCB and found ringing of more than 500 millivolts up and down. They are coincident with the retriggering of the timers. If I can stomp this out, the rest should work properly. 

I removed the FET transistor to gain access to the big ground pad underneath, then soldered an 18 gauge stranded wire to it which is connected to the IBM 1130 ground bus on the other side. With this in place, the ringing was substantially lower, as you can see from the scope output below:

Yellow is the +Storage Read signal, purple is the P1 parity bit, blue is the P2 parity bit and green is the ground where I monitored it. The bounce was cut down more than 50% and the result is no retriggering. I am convinced that it is time to make an updated version of the PCB with special attention to ground to minimize the ringing/bouncing.